one's complement of a number is obtained by invert­
ing each bit of the number.
In an arithmetic operation, a carry out of the in­
teger field changes the sign. However, in algebraic
left-shifting the sign bit does not change even if sig­
nificant high-order bits are shifted out.
Programming Note
The integer part of a signed fixed-point number may
be considered to represent a positive value, with the
sign representing a value of either zero or the maxi­
mum negative number.
Instructions
The general instructions and their mnemonics, for­
mats, and operation codes are listed in the following
table. The table also indicates when the condition
code is set and the exceptional conditions in operand
designations, data, or results that cause a program
interruption.
Note: In the detailed descriptions of the individual
instructions, the mnemonic and the symbolic oper­
and for the IBM System/370 assembly
language are shown with each instruction. For LOAD AND TEST, for example, LTR is the mne­
monic and R 1, R2 the operand designation.
Add
AR [RR]
o 8 12 15
A [RX]
5A
o 8 12 16 20 The second operand is added to the first operand,
and the sum is placed in the first-operand location.
31
Addition is performed by adding all 32 bits of
both operands. If the carry out of the sign-bit posi­
tion and the carry out of the high-order numeric bit
position agree, the sum is satisfactory; if they disa­
gree, an overflow occurs. The sign bit is not changed
after the overflow. A positive overflow yields a neg­
ative final sum, and a negative overflow results in a
positive sum. The overflow causes a program inter­
ruption when the fixed-point overflow mask bit is
one.
Resulting Condition Code:
o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow
Program Exceptions:
Access (fetch, operand 2 of A only)
Fixed-Point Overflow
Programming Note
In two's-complement notation a zero result is always
positive.
Add Hal/word
AH [RX]
4A
o 8 12 16 20 The second operand is added to the first operand,
and the sum is placed in the first-operand location.
The second operand is two bytes in length and is
considered to be a 16-bit signed integer.
31
The second operand is expanded to 32 bits before
the addition by propagating the sign-bit value
through the 16 high-order bit positions. The con­
tents of the second operand in main storage remain
unchanged.
Addition is performed by adding all 32 bits of
both operands. If the carry out of the sign-bit posi­
tion and the carry out of the high-order numeric bit
position agree, the sum is satisfactory; if they
disagree, an overflow occurs. The sign bit is not
changed after the overflow. A positive overflow
yields a negative final sum, and a negative overflow
results in a positive sum. The overflow causes a pro­
gram interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code: o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow
Program Exceptions:
Access (fetch, operand 2)
Fixed-Point Overflow
General Instructions 117
ADD
ADD
Name
ADD HALFWORD
ADD LOGIGAL ADD LOGIGAL Mnemonic
AR
A
AH
ALR
AL
NR
RR C RX C RX C RR C RX C RR C AND
AND N
RX C AND (character) AND (immediate) BRANCH AND LINK NC SS C NI SI C BALR RR
BAL BCR RX
RR BRANCH AND LINK BRANCH ON CONDITION BRANCH ON CONDITION BRANCH ON COUNT BRANCH ON COUNT BC RX BCTR RR BCT RX BRANCH ON INDEX HIGH BRANCH ON INDEX LOW OR BXH RS BXLE RS EQUAL COMPARE COMPARE COMPARE AND SWAP CR C CS COMPARE DOUBLE AND SWAP CDS COMPAREHALFWORD CH COMPARE iLOGICAL CLR COMPARE iLOGICAL CL COMPARE iLOGICAL (character) CLC COMPARE !LOGICAL (immediate) CLI COMPARE !LOGICAL CHAR- CLM ACTERS UNDER MASK COMPARE LOGICAL LONG CONVERT TO BINARY CONVERT TO DECIMAL DIVIDE DIVIDE EXCLUSIVE OR EXCLUSIVE OR EXCLUSIVE OR (character) EXCLUSIVE OR (immediate) EXECUTE CLCL CVB CVD DR
D
XR
X XC XI EX INSERT CHARACTER IC INSERT CHARACTERS UNDER ICM MASK LOAD LOAD LOAD ADDRESS LOAD AND TEST LOAD COMPLEMENT LOAD HALFWORD LOAD MULTIPLE LOAD NEGATIVE LOAD POSITIVE MONITOR GALL MOVE (character)
LR
L
LA
LTR LCR LH
LM
LNR
LPR MC MVC General-Instruction Summary (Part 1 of 2)
118 System/370 Principles of Operation
RR C RX C RS C RS C RX C RR C ,.AX C SS C SI C RS C RR C RX
RX
RR
RX
RR C RX C SS C SI C RX
RX RS C RR
RX
RX
RR C RR C RX RS RR C RR C SI SS A
A
A
A
A
A
A SW A SW A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A SP SP SP SP SP SP SP Characteristics
D IF IF IF IF IF IK IK IK $ II EX MO B
B
B
B
B
B
B
B
R
R
R
R
R
R
R
R
R
R H R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R Code 1A
5A
4A
1E
5E
14
54 ST D4 ST 94 05 45 07 47 06 46
86
87
19
59 ST BA ST BB
49
15
55
D5
95
BD OF 4F ST 4E
1D
5D
17
57 ST D7 ST 97
44
43
BF
18
58
41
12
13
48
98
11 10 AF ST D2
Previous Page Next Page