PTogranrnmdng The instruction MOVE LONG can be used for clear­
ing storage. Clearing can be accomplished by setting
the padding character to zero and the second oper­
:and count to zero.
When the first-operand count is zero, the opera­
tion consists in setting the condition code and setting
the high-order bytes of registers Rl and R2 to zero.
When the contents of the R 1 and R2 fields are the
same, the operation proceeds the same way as when
two distinct pairs of registers having the same con­
tents are specified. Condition code 0 is set, and pro­
tection and addressing exceptions are indicated when
called for by the operand designation.
Since the execution of MOVE LONG is interrup­
tible, the instruction cannot be used for situations
where the program must rely on uninterrupted exe­
cution of the instruction or on the interval timer not
being updated during the execution of the instruc­
tion. Similarly, the program should normally not let
the first operand of MOVE LONG include the loca­
tion of the instruction since the new contents of the
location may be interpreted for a resumption after
an interruption, or if the instruction is ref etched
without an interruption.
Special precautions must be taken if MOVE LONG is made the subject of EXECUTE. See the
programming notes under EXECUTE.
When the stop key is activated during the execu­
tion of MOVE LONG or COMPARE LOGICAL LONG, the CPU enters the stopped state at the
completion of the execution of the next unit of oper­
ation. Similarly, in the instruction-step mode, only a
unit of operation is performed. The amount of data
processed in a unit of operation depends on the
model and may depend on the particular condition
that causes the execution of the instruction to be
interrupted.
Move Numerics
MVN [SS] L--D_1 -L---.,L --1..--1· Bl--J........{I o 8 16 20 32 36 47
The low-order four bits of each byte in the second­
operand field, the numerics, are placed in the low­
order bit positions of the corresponding bytes in the
first-operand field. The high-order four bits of each
byte in the first-operand field remain unchanged.
Each operand field is processed left to right.
When the operands overlap, the result is obtained as
if the operands were processed one byte at a time
and each result byte were stored immediately after
the necessary operand byte is fetched.
Condition Code:
The code remains unchanged.
Program Exceptions: Access (fetch, operand 2; fetch and store, oper­
and 1)
Programming The execution of MVN consists in fetching the low- larder four bits of each byte in the first-operand
field, and subsequently storing the updated value of
the byte. These fetch and store accesses to a partic­
ular byte do not necessarily occur one immediately
after the other.
Move With Offset MVO [SS1
F1 I o 8 12 16 20 32 36 47
The second operand is placed to the left of and adja· cent to the low-order four bits of the first operand.
The low-order four bits of the first operand are
attached as low-order bits to the second operand,
the second operand bits are offset by four bit posi­
tions, and the result is placed in the first-operand
location. The first-operand and second-operand
bytes are not checked for valid codes.
The result is obtained as if the fields were pro­
cessed right to left. If necessary, the second operand
is extended with high-order zeros. If the first­
operand field is too short to contain all bytes of the
second operand, the remaining information is ig­
nored.
When the operands overlap, the result is obtained
as if the operands were processed one byte at a time
and each result byte were stored immediately after
the necessary operand bytes are fetched. The high­
order digit of each second-operand byte remains
available for the next result bytc and is not rc­
fetched.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2; fetch and store, oper­
and 1)
General Instructions 135

Programming Note
In the execution of MVO, the fetch and subsequent
store aecesses to the low-order byte of the first oper-'
and do not necessarily occur one immediately after
the other.
Move Zones L B, o 8 16 20 32 36 47
The high-order four bits of each byte in the second­ operand field (the zones) are placed in the high­ order four bit positions of the corresponding bytes in
the first-operand field. The low-order four bits of
each byte in the first-operand field remain un­ changed.
Each operand field is processed left to right.
When the operands overlap, the result is obtained as
if the operands were processed one byte at a time
and each result byte were stored immediately after
the necessary operand byte is fetched. Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2; fetch and store, oper­ and 1)
Programming Note
The execution of MVZ consists in fetching the high­ order four bits of each byte in the first-operand
field, and subsequently storing the updated value of
the byte. These fetch and store accesses to a particu­ lar byte do not necessarily occur one immediately
after the other.
MUltiply
MR Rl,R2 [RR]
136 System/370 Principles of Operation The product of the multiplier (the second operand)
and the multiplicand (the first operand) replaces the
mUltiplicand.
Both mUltiplier and multiplicand are 32-bit signed
integers. The product is always a 64-bit signed inte­ ger and occupies an even-odd register pair. Because
the multiplicand is replaced by the product, the R 1
field of the instruction must refer to an even­ numbered register. A specification exception occurs
when R
1 is odd. The multiplicand is taken from the
odd register of the pair. The contents of the even­ numbered register replaced by the product are ig­ nored, unless the register contains the multiplier. An
overflow cannot occur.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of M only)
Specification
Programming Note
The significant part of the product usually occupies
62 bits or fewer. Only when two maximum negative
numbers are multiplied are 63 significant product
bits formed. Since two's-complement notation is
used, the sign bit is extended right until the first sig­ nificant product digit is encountered.
Multiply Hal/word
MH Rl,D2(X2,B2) [RX]
4C
o 8 12 16 20 31
The product of the multiplier (second operand) and
multiplicand (first operand) replaces the multipli­ cand. The second operand is two bytes in length and
is considered to be a 16-bit signed integer.
Both multiplicand and product are 32-bit signed
integers and may be located in any general register.
The 16-bit multiplier is expanded to 32 bits before
multiplication by propagating the sign-bit value
through the 16 high-order bit positions. The multipli­
cand is replaced by the low-order part of the prod­
uct. The bits to the left of the 32 low-order bits are
not tested for significance; no overflow indication is
given.