When the operands overlap, the result is obtained
as if each result byte were stored immediately after
the necessary operand bytes are fetched. Two
second-operand bytes are needed for each result byte, except for the rightmost byte of the result
field, which requires only the rightmost second­
operand byte.
Condition Code:
The code remains unchanged. Program Exceptions:
Access (fetch, operand 2; store, operand 1)
Programming Notes
The PACK instruction may be used to interchange
the two hex digits in one byte by specifying a zero in
the Lt and L2 fields and the same address for both
operands.
To remove the zones of all bytes of a field, in­
cluding the low-order byte, both operands must be
extended with a dummy byte in the low-order posi­
tion, which subsequently is ignored in the result
field.
Set Program Mask SPM Rt [RR]
Bits 2-7 of the general register specified by the R t
field repllace the condition code and the program
mask bits of the current PSW. Bits 12-15 of the in­
struction are ignored.
Bits 0, 1, and 8-31 of the register specified by the
Rt field are ignored. The contents of the register
specified by the Rt field remain unchanged.
The instruction permits setting of the condition
code andl the mask bits in either the problem or su­
pervisor state. Conditim' Code:
The code is set according to bits 2 and 3 of the
register specified by Rt.
Program Exceptions:
None
Programming Note
Bits 2-7 of the general register may have been load­
ed from the PSW by BRANCH AND LINK.
138 System/370 Principles of Operation
Shift Left Double
SLDA [RS]
o 8 12 16 20 31
The double-length integer part of the first operand is
shifted left the number of bits specified by the
second-operand address. Bits 12-15 of the instruc­
tion are ignored.
The Rt field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rt is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par­
ticipate in the shift in the same manner as the other
integer bits. Zeros are supplied to the vacated posi­
tions of the registers.
If a bit unlike the sign bit is shifted out of bit posi­
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the
fixed-point overflow mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Exceptions:
Specification
Fixed-Point Overflow Programming Notes
The eight shift instructions provide the following
three pairs of alternatives: left or right, single or
double, and algebraic or logical. The algebraic shifts
differ from the logical shifts in that, in the algebraic
shifts, overflow is recognized, the condition code is
set, and the high-order bit participates as a sign.
The maximum shift amount which can be speci­
fied is 63. For algebraic shifts this is sufficient to
shift out the entire integer field. Since 64 bits partici­
pate in the double-logical shifts, the entire register
contents cannot be shifted out.
A zero shift amount in the two algebraic double­
shift operations provides a double-length sign and
magnitude test.
The base register participating in the generation
of the second-operand address permits indirect spec­
ification of the shift amount. A zero in the B2 field
indicates the absence of indirect shift specification.
Shift Left Double Logical
SLDL [RS]
L __ o 8 12 16 20 31
The double-length first operand is shifted left the
number of bits specified by the second-operand ad­
dress. Bits 12-15 of the instruction are ignored. Rl field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. High-order bits are shifted out of the even­
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Left Single
SLA Rl,D2(B2) [RS]
88
o 8 12 16 20 31
The integer part of the first operand is shifted left
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad-­ dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
left shift. Zeros are supplied to the vacated low­
order register positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a pro­
gram interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
For numbers with an absolute value of less than 230, a left shift of one bit position is equivalent to multi­
plying the number by two.
Shift amounts from 31-63 cause the entire integer
to be shifted out of the register. When the entire
integer field for a positive number has been shifted
out, the register contains a value of zero. For a nega­
tive number, the register contains a value of _231.
Shift Left Single Logical
SLL Rl,D2(B2) [RS]
89
o 8 12 16 20 31
The first operand is shifted left the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. High-order bits are shifted out without inspec­
tion and are lost. Zeros are supplied to the vacated
low-order register positions.
Condition Code:
The code remains unchanged.
Program Exceptiom: None
General Instructions 139
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