When the operands overlap, the result is obtained
as if each result byte were stored immediately after
the necessary operand bytes are fetched. Two
second-operand bytes are needed for eachresult byte, except for the rightmost byte of the result
field, which requires only the rightmost second
operand byte.
Condition Code:
The code remains unchanged.Program Exceptions:
Access (fetch, operand 2; store, operand 1)
Programming Notes
ThePACK instruction may be used to interchange
the two hex digits in one byte by specifying a zero in
the Lt and L2 fields and the same address for both
operands.
To remove the zones of all bytes of a field, in
cluding the low-order byte, both operands must be
extended with a dummy byte in the low-order posi
tion, which subsequently is ignored in the result
field.
SetProgram Mask SPM Rt [RR]
Bits 2-7 of the general register specified by the R t
field repllace the condition code and the program
mask bits of the currentPSW. Bits 12-15 of the in
struction are ignored.
Bits0, 1, and 8-31 of the register specified by the
Rt field are ignored. The contents of the register
specified by the Rt field remain unchanged.
The instruction permits setting of the condition
code andl the mask bits in either the problem or su
pervisor state.Conditim' Code:
The code is set according to bits 2 and 3 of the
register specified by Rt.
Program Exceptions:
None
Programming Note
Bits 2-7 of the general register may have been load
ed from thePSW by BRANCH AND LINK.
138System/370 Principles of Operation
Shift Left Double
SLDA [RS]
o 8 12 1620 31
The double-length integer part of the first operand is
shifted left the number of bits specified by the
second-operand address. Bits 12-15 of the instruc
tion are ignored.
The Rt field of the instruction specifies an even
odd pair of registers and must designate an even
numbered register. When Rt is odd, a specification
exception is recognized.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par
ticipate in the shift in the same manner as the other
integer bits. Zeros are supplied to the vacated posi
tions of the registers.
If a bit unlike the sign bit is shifted out of bit posi
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the
fixed-point overflow mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3Overflow Program Exceptions:
Specification
Fixed-PointOverflow Programming Notes
The eight shift instructions provide the following
three pairs of alternatives: left or right, single or
double, and algebraic or logical. The algebraic shifts
differ from the logical shifts in that, in the algebraic
shifts, overflow is recognized, the condition code is
set, and the high-order bit participates as a sign.
The maximum shift amount which can be speci
fied is 63. For algebraic shifts this is sufficient to
shift out the entire integer field. Since 64 bits partici
pate in the double-logical shifts, the entire register
contents cannot be shifted out.
as if each result byte were stored immediately after
the necessary operand bytes are fetched. Two
second-operand bytes are needed for each
field, which requires only the rightmost second
operand byte.
Condition Code:
The code remains unchanged.
Access (fetch, operand 2; store, operand 1)
Programming Notes
The
the two hex digits in one byte by specifying a zero in
the Lt and L2 fields and the same address for both
operands.
To remove the zones of all bytes of a field, in
cluding the low-order byte, both operands must be
extended with a dummy byte in the low-order posi
tion, which subsequently is ignored in the result
field.
Set
Bits 2-7 of the general register specified by the R t
field repllace the condition code and the program
mask bits of the current
struction are ignored.
Bits
Rt field are ignored. The contents of the register
specified by the Rt field remain unchanged.
The instruction permits setting of the condition
code andl the mask bits in either the problem or su
pervisor state.
The code is set according to bits 2 and 3 of the
register specified by Rt.
Program Exceptions:
None
Programming Note
Bits 2-7 of the general register may have been load
ed from the
138
Shift Left Double
SLDA [RS]
o 8 12 16
The double-length integer part of the first operand is
shifted left the number of bits specified by the
second-operand address. Bits 12-15 of the instruc
tion are ignored.
The Rt field of the instruction specifies an even
odd pair of registers and must designate an even
numbered register. When Rt is odd, a specification
exception is recognized.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par
ticipate in the shift in the same manner as the other
integer bits. Zeros are supplied to the vacated posi
tions of the registers.
If a bit unlike the sign bit is shifted out of bit posi
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the
fixed-point overflow mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3
Specification
Fixed-Point
The eight shift instructions provide the following
three pairs of alternatives: left or right, single or
double, and algebraic or logical. The algebraic shifts
differ from the logical shifts in that, in the algebraic
shifts, overflow is recognized, the condition code is
set, and the high-order bit participates as a sign.
The maximum shift amount which can be speci
fied is 63. For algebraic shifts this is sufficient to
shift out the entire integer field. Since 64 bits partici
pate in the double-logical shifts, the entire register
contents cannot be shifted out.