A zero shift amount in the two algebraic double
shift operations provides a double-length sign and
magnitude test.
The base register participating in the generation
of the second-operand address permits indirect spec
ification of the shift amount. A zero in the B2 field
indicates the absence of indirect shift specification.
Shift Left Double Logical
SLDL [RS]
L __ o 8 12 16 20 31
The double-length first operand is shifted left the
number of bits specified by the second-operand ad
dress. Bits 12-15 of the instruction are ignored. Rl field of the instruction specifies an even
odd pair of registers and must designate an even
numbered register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. High-order bits are shifted out of the even
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Left Single
SLA Rl,D2(B2) [RS]
88
o 8 12 1620 31
The integer part of the first operand is shifted left
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used toad- dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
left shift. Zeros are supplied to the vacated low
order register positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a pro
gram interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
For numbers with an absolute value of less than230, a left shift of one bit position is equivalent to multi
plying the number by two.
Shift amounts from 31-63 cause the entire integer
to be shifted out of the register. When the entire
integer field for a positive number has been shifted
out, the register contains a value of zero. For a nega
tive number, the register contains a value of _231.
Shift Left Single Logical
SLL Rl,D2(B2) [RS]
89
o 8 12 1620 31
The first operand is shifted left the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. High-order bits are shifted out without inspec
tion and are lost. Zeros are supplied to the vacated
low-order register positions.
Condition Code:
The code remains unchanged.
ProgramExceptiom: None
General Instructions 139
shift operations provides a double-length sign and
magnitude test.
The base register participating in the generation
of the second-operand address permits indirect spec
ification of the shift amount. A zero in the B2 field
indicates the absence of indirect shift specification.
Shift Left Double Logical
SLDL [RS]
L __
The double-length first operand is shifted left the
number of bits specified by the second-operand ad
dress. Bits 12-15 of the instruction are ignored.
odd pair of registers and must designate an even
numbered register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. High-order bits are shifted out of the even
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Left Single
SLA Rl,D2(B2) [RS]
88
o 8 12 16
The integer part of the first operand is shifted left
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
left shift. Zeros are supplied to the vacated low
order register positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a pro
gram interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
For numbers with an absolute value of less than
plying the number by two.
Shift amounts from 31-63 cause the entire integer
to be shifted out of the register. When the entire
integer field for a positive number has been shifted
out, the register contains a value of zero. For a nega
tive number, the register contains a value of _231.
Shift Left Single Logical
SLL Rl,D2(B2) [RS]
89
o 8 12 16
The first operand is shifted left the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. High-order bits are shifted out without inspec
tion and are lost. Zeros are supplied to the vacated
low-order register positions.
Condition Code:
The code remains unchanged.
Program
General Instructions 139