A zero shift amount in the two algebraic double­
shift operations provides a double-length sign and
magnitude test.
The base register participating in the generation
of the second-operand address permits indirect spec­
ification of the shift amount. A zero in the B2 field
indicates the absence of indirect shift specification.
Shift Left Double Logical
SLDL [RS]
L __ o 8 12 16 20 31
The double-length first operand is shifted left the
number of bits specified by the second-operand ad­
dress. Bits 12-15 of the instruction are ignored. Rl field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. High-order bits are shifted out of the even­
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Left Single
SLA Rl,D2(B2) [RS]
88
o 8 12 16 20 31
The integer part of the first operand is shifted left
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad-­ dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
left shift. Zeros are supplied to the vacated low­
order register positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a pro­
gram interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow
Program Exceptions:
Fixed-Point Overflow
Programming Note
For numbers with an absolute value of less than 230, a left shift of one bit position is equivalent to multi­
plying the number by two.
Shift amounts from 31-63 cause the entire integer
to be shifted out of the register. When the entire
integer field for a positive number has been shifted
out, the register contains a value of zero. For a nega­
tive number, the register contains a value of _231.
Shift Left Single Logical
SLL Rl,D2(B2) [RS]
89
o 8 12 16 20 31
The first operand is shifted left the number of bits
specified by the second-operand address. Bits 12-15
of the instruction are ignored.
The second-operand address is not used to ad­
dress data; its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 32 bits of the first operand participate in the
shift. High-order bits are shifted out without inspec­
tion and are lost. Zeros are supplied to the vacated
low-order register positions.
Condition Code:
The code remains unchanged.
Program Exceptiom: None
General Instructions 139
Shift Right Double SRDA The double-length integer part of the first operand is
shifted right the number of places specified by the
second-operand address. Bits 12-15 of the instruc­
tion are ignored.
The R 1 field of the instruction specifies an even­
odd pair of registers and must designate an even­ register. When Rl is odd, a specification
exception is recognized.
The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The first operand is treated as a number with 63
integer bits and a sign in the sign position of the
even register. The sign remains unchanged. The
high-order position of the odd register contains an
integer bit, and the contents of the odd register par­
ticipate in the shift in the same manner as the other
integer bits. The low-order bits are shifted out with­
out inspection and are lost. Bits equal to the sign are
supplied to the vacated positions of the registers. Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Specification
Shift llight Double Logical SRDL Rl,D2(B2) [RS] The double-length first operand is shifted right the
number of bits specified by the second-operand ad­
dress. Bits 12-15 of the instruction are ignored.
The Rl field of the instruction specifies an even­
odd pair of registers and must designate an even­
numbered register. When Rl is odd, a specification
exception is recognized. 140 System/370 Principles of Operation The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
All 64 bits of the first operand participate in the
shift. Low-order bits are shifted out of the odd­
numbered register without inspection and are lost.
Zeros are supplied to the vacated positions of the
registers.
Condition Code:
The code remains unchanged.
Program Exceptions:
Specification
Shift Right Single
8A
o 8 12 16 20 31
The integer part of the first operand is shifted right
the number of bits specified by the second-operand
address. Bits 12-15 of the instruction are ignored.
The second-operand address is not used to ad­
dress its low-order six bits indicate the number
of bit positions to be shifted. The remainder of the
address is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: None
Programming Note
A right shift of one bit position is equivalent to divi­
sion by two with rounding downward. When an even
number is shifted right one position, the value of the
field is that obtained by dividing the value by 2.
When an odd number is shifted right one position,
the value of the field is that obtained by dividing the
next lower number by two. For example, +5 shifted
right by one bit position yields + 2, whereas -5 yields
-3.
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