Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
ing, and other system-related functions.
The: physical makeup of the CPU controls in the
various models of the System/370 may be different,
but the logical function remains the same. The result
of executing a valid instruction is the same for each
modeL Tht: CPU, in executing instructions, can process
binary integers and floating-point numbers of fixed
length, decimal integers of variable length, and logi­
cal information of either fixed or variable length. Processing may be in parallel or in series; the width
of the processing elements, the multiplicity of the
shifting paths, and the degree of simultaneity in per­
forming the different types of arithmetic differ from
one CPU to another without affecting the logical
results.
Instructions which the CPU executes fall into five
classes: system-control, general, decimal, floating­
point, and input/output instructions. The system­
control and input/output instructions are privileged
instructions that can be executed only when the CPU is in the supervisor state. The general instruc­
tions are used in performing fixed-point, logical,
branching, and other control and data-manipulation
operations. The decimal instructions operate on data
in the decimal format, and the floating-point instruc­
tions on data in the floating-point format.
To perform its functions, the CPU uses a certain
amount of internal storage other than main storage.
Portions of this storage can be designated. by the
program, such as the current program status word (PS\\T), the general registers, the floating-point reg­
isters, the control registers, the prefix register, and
registers associated with the timing facilities.
The current PSW contains information used to
control instruction sequencing and to hold and indi­
cate the states of the system in relation to the pro­
gram currently being executed. Registers associated
with the timing facilities contaJn the time-of-day
clock:, the clock comparator, and the CPU timer. The
genelral, floating-point, and control registers are dis­ cussed separately in the following paragraphs. The
instruction operation code determines which type of
register is to be used in an operation.
General Registers
The CPU can address information in 16 general
registers. The general registers can be used as base­
address registers and index registers in address arith­
metic and as accumulators in general arithmetic and logical operations. Each register contains 32 bits. The gene:ral registers are identified by the numbers 0-15 16 System/370 Principles of Operation
and are designated by a four-bit R field in an instruc­
tion (see accompanying illustration). Some instruc­
tions provide for addressing multiple general registers
by having several R fields.
For some operations, two adjacent general regis­
ters are coupled together, providing a 64-bit format.
In these operations, the program must designate an
even-numbered register, which contains the high­
order bits. The next higher numbered register con­
tains the low-order bits.
In addition to their use as accumulators in general
arithmetic and logical operations, 15 of the 16 gen­
eral registers are also used as base-address and index
registers in address generation. In these cases, the
registers are designated by a four-bit B field or X
field in an instruction. A value of zero in the X or B
field specifies no index or base is to be applied, and,
thus, general register 0 cannot be designated as con­
taining an index or base address.
Floating-Point Registers
Four floating-point registers are available for
floating-point operations. They are identified by the
numbers 0, 2, 4, and 6 (see illustration). Each
floating-point register contains 64 bits and can con­
tain either a short (32-bit) or a long (64-bit) floating­
point operand. A short operand occupies the high­
order bit positions of a floating-point register. The
low-order portion of the register is ignored and re­
mains unchanged in arithmetic calling for short ope­
rands. Two pairs of adjacent floating-point registers
can be used for extended operands: registers 0, 2,
and registers 4,6. Each of these pairs provides a 128-
bit format.
Control Registers
The CPU can designate 16 control registers, each 32
bit positions in length. The bit positions in the regis­
ters are assigned to particular facilities in the system,
such as program-event recording, and are used either
to specify whether an operation can take place or to
provide special information required by the facility. On any particular model, only those bit positions are
necessarily provided which are required by the in­
stalled facilities.
The control registers are identified by the num­
bers 0-15 and are designated by a four-bit R field in
the instructions LOAD CONTROL and STORE CONTROL. Multiple control registers can be ad­
dressed by these instructions.

R
Field Reg. Number Control Registers r----- 32 General Registers r----- 32 Bits Floating-Point Registers I ........ ----64 Bits 0000 0 0001 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14
1111 15
Note: The braces indicate that the two registers may be coupled as a double-register
pair, designated by the R
field of the lower-numbered register. For example, the
general register pair 0 and 1 is designated by the R
field of register O. General, Floating-Point, and Control Registers
Input and Output
Input/output (I/O) operations involve the transfer
of information between main storage and an I/O device. I/O devices attach to channels, which con­
trol the transfer of data between the devices and
main storage.
Channels
The channel connects with the CPU and main stor­
age and, usually by means of the I/O interface, with
control units. The channel relieves the CPU of the
burden of communicating directly with I/O devices
and permits data processing to proceed concurrently
with I/O operations.
A channel may be an independent unit, complete
with necessary logical and storage capabilities, or it
may time-share CPU facilities and be physically
integrated with the CPU. In either case, channel
functions are identical. Channels may be implement­
ed, however, to have different maximum data­
transfer capabilities. System/370 has three types of channels: byte­
multiplexer, block-multiplexer, and selector chan­
nels.
Input/Output Interface
For most devices, communication between the con­
trol unit and the channel takes place over a connec­
tion called the I/O interface. The I/O interface System Organization 17