LCDR Rl,R2
[RR, Long Operands] The second operand is placed in the first-operand
location with the sign changed to the opposite value.
The sign bit is inverted, even if the fraction is
zero. The eharacteristic and fraction are not
changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed)
Specification
Load Negative
LNER Rl,R2
[RR, Short Operands] LNDR Rl,R2
[RR, Long Operands] o 8 12 15
The second operand is placed in the first-operand
location with the sign made minus.
The sign bit is made one, even if the fraction is
zero. The characteristic and fraction are not
changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
166 System/370 Principles of Operation Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 -
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed)
Specification
Load Positive LPER Rl,R2
[RR, Short Operands] 30 o 8 12 15 LPDR Rl,R2
[RR, Long Operands] 20 o 8 12 15
The second operand is placed in the first-operand
location with the sign made plus.
The sign bit is made zero. The characteristic and
fraction are not changed.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 -
2 Result is greater than zero
3 -
Program Exceptions:
J Operation (if the floating-point feature is not
installed)
Specification
Load Rounded
LRER Rl,R2
[RR, Long Operand 2, Short Operand 1]
35
o 8 12 15

LRDR Rl,R2
[RR, Extended Operand 2, Long Operand 1]
25
o 8 12 15
The second operand is rounded to the next smaller
format, and the result is placed in the first-operand
location.
Rounding consists in adding a one in bit position
32 or 72 of the long or extended second operand,
respectively, and propagating the carry, if any, to the
left. For both cases, the sign of the fraction is ig­
nored, and addition is performed as if the fractions
were positive.
If rounding causes a carry out of the high-order
digit position of the fraction, the fraction is shifted
right one digit position, and the characteristic is in­
creased by one.
The sign of the result is the same as the sign of
the second operand. No normalization takes place.
An exponent-overflow exception is recognized
when shifting the fraction right causes the character­
istic to exceed 127. The operation is completed by
loading a number whose characteristic is 128 less
than the correct value, and a program interruption
for exponent overflow occurs. The result is normal­
ized, and the sign and fraction remain correct.
Exponent-underflow and significance exceptions
cannot occur.
The Rl field must designate register 0, 2, 4, or 6;
the R2 field of LRER must designate register 0, 2, 4,
or 6; and the R2 field of LRDR must designate reg­
ister ° or 4. Otherwise, a specification exception is
recognized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the extended-precision floating­
point feature is not installed)
Specification
Exponent Overflow
Multiply
MER Rl,R2
[RR, Short Multiplier and Multiplicand,
Long Product]
3C
o 8 12 15
ME Rl,D2(X2,B2)
[RX, Short Multiplier and Multiplicand,
Long Product]
o 8 12 16
MDR
[RR, Long Operands]
o 8 12 15
MD Rl,D2(X2,B2)
[RX, Long Operands]
6C 20 o 8 12 16 20 MXDR Rl,R2
[RR, Long Multiplier and Multiplicand,
Extended Product 1
o 8 12 15
MXD Rl,D2(X2,B2)
[RX, Long Multiplier and Multiplicand,
Extended Product 1
67
o 8 12 16 20 MXR Rl,R2
[RR, Extended Operands]
o 8 12 15
31
31
31
The normalized product of the second operand (the
multiplier) and the first operand (the multiplicand) is
placed in the first-operand location.
Floating-Point Instructions 167