SWR Rl,R2
[RR, Long Operands] o 8 12 15
SW Rl,D2(X2,B2)
[RX, Long Operands] o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the unnormalized difference is placed in
the first··operand location.
The execution of SUBTRACT UNNORNlAL­ IZED is identical to that of ADD UNNORMAL- 170 System/370 Principles of Operation IZED, except that the second operand participates in
the operation with its sign bit inverted.
The Rl and R2 fields must designate register 0, 2,
4, or otherwise,. a specification exception is recog­
nized.
Resulting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 - Program Exceptions: Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of SU and SW only)
Specification
Significance
Machine-Check Detection .
Recovery Mechanisms .
Redundancy Correction CPU Retry
Unit Deletion Handling of Machine Checks
Contents Handling of Invalid CBC in Storage Programmed Validation of Storage Handling of Invalid CBC in Keys in Storage Handling of Invalid CBC in Registers. Validation of Registers .
Check-Stop State Machine-Check Interruption Conditions Repressible Conditions .
Exigent Conditions .
Machine-Check Interruption Interruption Action. Point of Interruption Machine-Check Logout.
Machine-Check Handling
Machine-Check Extended Interruption Information Machine-Check Interruption Code.
171
172
172
172
172
172
172
173
173
173
173
175
175
175
175
175
175
176
177
177
178
178
179
179 180 181
181
181
181
181
182
182
183 Subclass .
Time of Interruption Occurrence Storage Error Type .
Machine-Check I nterruption Code Validity Bits.
Machine-Check Extended Logout Length
Machine-Check Control Registers . Control Register 14 .
Check-Stop Control Logout Controls. Machine-Check Subclass Masks Control Register 15 . Summary of Machine-Check Masking
The System/370 machine-check handling mecha­
nism provides extensive machine-malfunction detec­
tion to ensure the integrity of system operation, auto­
matic recovery from some malfunctions, and report­
ing by means of a machine-check interruption to
assist in maintenance and repair and in program
damage-assessment and recovery.
Machine-Check Detection
Machine-check detection mechanisms may take
many forms, especially in control functions for arith­
metic and logical processing, addressing, sequencing,
and execution. For program-addressable informa­
tion, detection is normally accomplished by encoding
redundancy into the information in such a manner
that most failures in the retention or transmission of
the information will result in an invalid code. The
encoding normally takes the form of one or more
redundancy bits appended to a group of information
bits. These redundancy bits are referred to as "check bits." The group of data bits and the associated
check bits are called the "checking block. " The inclusion of a single check bit in the checking
block allows the detection of any single-bit failure
within the checking block. In this arrangement, the
checking bit is sometimes referred to as a "parity bit. " In other arrangements, a group of check bits is
included, increasing the checking power and, in some
cases, providing sufficient redundancy to permit
both detection and correction.
For checking purposes, the entire content of a
checking block, including the redundancy, is called a
"checking block code" (CBC). When a CBC com­
pletely meets the checking requirements (that is, no
failure is detected), it is said to be valid. When both
detection and correction are provided and a CBC is
not valid but satisfies the checking requirements for
correction (the failure is correctable), it is said to be
near-valid. When a CBC does not satisfy the check­
ing requirements (the failure is uncorrectable), it is
said to be invalid.
Machine-Check Handling 171
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