Check-Stop State
In certain situations it is impossible or undesirable to
continue operation when a machine error occurs. In
these cases, theCPU may enter the check-stop state.
When theCPU is in the check-stop state, the
condition is indicated by an error indicator, an audi
ble signal, or both. The system indicator is off, but
the state of the manual indicator depends on the
model. The exact indication of check-stop state is
model-dependent and is described in theSystem Library (SL) publication for the CPU. The machine enters the check-stop, state only as a
result of exigent conditions. The machine may be
removed from the check-stop state byCPU reset.
When theCPU is in the check-stop state, instruc
tions and interruptions are not executed. The inter
val timer is not updated, and channel operations may
be suspended. TheTOD clock is not normally affect
ed by check-stop state. TheCPU timer mayor may
notrun-in check-stop state, depending on the error
and the model. TheCPU cluster meter does not run,
and the clock-out and metering-out lines are down.
The stop key and start key are not operative during
this state.
In a multiprocessing system, aCPU entering the
check-stop state generates a request for a
malfunction-alert external interruption to allCPUs configured to this CPU. Machine-Check Interruption
Conditions
Equipment malfunctions and other conditions re
sponsible for machine-check interruptions are re
ferred to as machine-check interruption conditions.
Two major types of conditions are identified: exigent
conditions and repressible conditions.
Repressible Conditions
Repressible conditions are those in which the se
quential processing capability of theCPU has not
been affected. Repressible conditions can be delayed
until the completion of the current instruction, and
in most cases, even longer, without affecting the
integrity of theCPU operation. Repressible condi
tions are of three types: recovery, alert, and repress'
ible damage. Each has one or more subclasses as
follows:
A hardware malfunction successfully corrected or
circumvented without loss of system integrity is
called a recovery condition. Depending on the model
and the type of malfunction, some recovery condi
tions may be discarded and not reported. Recovery
conditions that are reported are grouped in one sub
class, system recovery.
Page ofGA22-70004 Revised September 1, 1975
By TNL: GN22-0498
A machine-check interruption condition not di
rectly related to a hardware malfunction is called an
alert condition. The alert conditions contain two
subclasses: degradation and warning.
A hardware malfunction resulting in the loss of
integrity of a process in .the system but not directly
affecting the sequentialCPU operation is called a
repressible damage condition. Repressible damage
conditions are divided into three subclasses, identify
ing the process affected: timer damage, timing
facility damage, and external damage.
Exigent Conditions
Exigent conditions are those in which direct damage
has occurred to theCPU operation, and the current
instruction or interruption cannot safely continue.
Exigent conditions are divided into two subclasses:
instruction-processing damage, and system damage.
Malfunctions which cannot be isolated to a specific
process are indicated as system damage.
Machine-Check Interruption
The machine-check interruption provides a means of
reporting equipment malfunction and certain exter
nal disturbances, and it supplies the program with
information about the extent of the resultant damage
and the location and nature of the cause.
Interruption Action
A machine-check interruption causes thePSW re
flecting the point of interruption to be stored as the
machine-check oldPSW at location 48; extended
machine-check interruption information is stored,
consisting of the information in all the control regis
ters, general registers, floating-point registers,CPU timer, clock comparator, a region code, and a failing
storage address. Then the machine-check interrup
tion code (MCIC) of eight bytes is stored. A newPSW is fetched from location 112. Additionally,
sometime before the storing of the machine-check
interruption code, one or several machine-check
logouts may have occurred. The machine-generated
addresses to reference the old and newPSW, the
interruption code and extended interruption informa
tion, and the fixed logout area are all real addresses.
The extended machine-check logout address is also a
real address. If the machine-check interruption code
cannot be stored successfully or the newPSW can
not befetChed successfully, the CPU enters the
check-stop state if the check-stop control bit is one.
A machine-check interruption due to a repressible
machine-check condition can occur only when bothPSW bit 13 and the associated subclass mask are
ones. A repressible machine-check interruption does
not terminate the execution of the current instruc-
Machine-Check Handling 175
In certain situations it is impossible or undesirable to
continue operation when a machine error occurs. In
these cases, the
When the
condition is indicated by an error indicator, an audi
ble signal, or both. The system indicator is off, but
the state of the manual indicator depends on the
model. The exact indication of check-stop state is
model-dependent and is described in the
result of exigent conditions. The machine may be
removed from the check-stop state by
When the
tions and interruptions are not executed. The inter
val timer is not updated, and channel operations may
be suspended. The
ed by check-stop state. The
not
and the model. The
and the clock-out and metering-out lines are down.
The stop key and start key are not operative during
this state.
In a multiprocessing system, a
check-stop state generates a request for a
malfunction-alert external interruption to all
Conditions
Equipment malfunctions and other conditions re
sponsible for machine-check interruptions are re
ferred to as machine-check interruption conditions.
Two major types of conditions are identified: exigent
conditions and repressible conditions.
Repressible Conditions
Repressible conditions are those in which the se
quential processing capability of the
been affected. Repressible conditions can be delayed
until the completion of the current instruction, and
in most cases, even longer, without affecting the
integrity of the
tions are of three types: recovery, alert, and repress'
ible damage. Each has one or more subclasses as
follows:
A hardware malfunction successfully corrected or
circumvented without loss of system integrity is
called a recovery condition. Depending on the model
and the type of malfunction, some recovery condi
tions may be discarded and not reported. Recovery
conditions that are reported are grouped in one sub
class, system recovery.
Page of
By TNL: GN22-0498
A machine-check interruption condition not di
rectly related to a hardware malfunction is called an
alert condition. The alert conditions contain two
subclasses: degradation and warning.
A hardware malfunction resulting in the loss of
integrity of a process in .the system but not directly
affecting the sequential
repressible damage condition. Repressible damage
conditions are divided into three subclasses, identify
ing the process affected: timer damage, timing
facility damage, and external damage.
Exigent Conditions
Exigent conditions are those in which direct damage
has occurred to the
instruction or interruption cannot safely continue.
Exigent conditions are divided into two subclasses:
instruction-processing damage, and system damage.
Malfunctions which cannot be isolated to a specific
process are indicated as system damage.
Machine-Check Interruption
The machine-check interruption provides a means of
reporting equipment malfunction and certain exter
nal disturbances, and it supplies the program with
information about the extent of the resultant damage
and the location and nature of the cause.
Interruption Action
A machine-check interruption causes the
flecting the point of interruption to be stored as the
machine-check old
machine-check interruption information is stored,
consisting of the information in all the control regis
ters, general registers, floating-point registers,
storage address. Then the machine-check interrup
tion code (MCIC) of eight bytes is stored. A new
sometime before the storing of the machine-check
interruption code, one or several machine-check
logouts may have occurred. The machine-generated
addresses to reference the old and new
interruption code and extended interruption informa
tion, and the fixed logout area are all real addresses.
The extended machine-check logout address is also a
real address. If the machine-check interruption code
cannot be stored successfully or the new
not be
check-stop state if the check-stop control bit is one.
A machine-check interruption due to a repressible
machine-check condition can occur only when both
ones. A repressible machine-check interruption does
not terminate the execution of the current instruc-
Machine-Check Handling 175