stored is the address that is used to reference: storage
after dynamic address translation and prefixing, if
any, have been applied.
Region Code: The word at location 252 contains
model-dependent information which more specifical­
ly defines the location of the error. For example, it
may contain a model-dependent address of the unit
causing an external damage or recovery report.
Register Save Area: On all machine-check interrup­
tions, the addressable registers are saved sequentially
in storage. Floating-point registers 0, 2, 4, and 6 are
stored starting at location 352; when the floating­
point feature is not installed, these locations are left
unchanged. General registers 0-15 are stored start­
ing at location 384, and control registers 0-15 are
stored starting at location 448. The information
stored for control-register positions not associated
with an installed feature is unpredictable.
Machijne-Check Interruption Code
The machine-check interruption code (MCIC) is an
eight-byte field starting at location 232 and has the
format shown in the illustration.
Bits in the machine-check interruption code which
are not assigned, or not implemented by a particular
model, are stored as zeros.
Subclass
Bits 0-5, 7, and 8 identify the machine-check condi­
tions causing the interruption. At least one bit will
be stored as a one in the subclass field. When multi­
ple errors have occurred, several bits may be set to
ones.
System Damage (SD): Bit 0, when one, indicates
that damage has occurred which cannot be isolated
to one or more of the less severe machine-check
damage subclasses.
Instruction Processing Damage (PD): Bit 1, when
one, indicates that a malfunction has been detected
in the processing of instructions. The exact meaning
of bit 1 depends on the setting of the backed-up bit,
bit 14.
When the backed-up bit is one, a valid instruction
address stored in the machine-check old PSW, and
the other machine status saved, point to the begin­
ning of a unit of operation prior to the point at
which the damage would have occurred. When the
backed-up bit is one and all status is indicated as
valid, the machine has successfully returned to a
checkpoint prior to the malfunction, and no damage
has yet occurred.
When the backed-up bit is zero, a valid instruc­
tion address points to the beginning of an instruction
containing a unit of operation beyond the damaged
unit of operation. For damage to be indicated as
instruction processing damage, the damaged instruc­
tion and the point of interruption must not be sepa­
rated by an interruption or by a LOAD PSW instruc­
tion, and the extent of the damage must fall within
one or more of the following categories:
1. The damaged area still contains invalid CBC.
2. The damaged area lies within tIle destination
operand of the instruction.
3. The damaged area lies within the general regis­
ters, floating-point registers, control registers,
or PSW. System Recovery (SR): Bit 2, when one, indicates
that malfunctions were detected but have been suc­
cessfully corrected or circumvented without the loss
of system integrity. CPU-detected malfunctions are
reported as system recovery only if the CPU success­
fully completes the operation or unit of operation in
which the malfunction was detected. Some 1/0- detected damage conditions may result in a system
recovery condition in addition to the 110 interrup­
tion. The indication of system recovery does not G 0 0 0 0 0 0 0 0 0 0 0 I I ...L.1 ___ M_a_ch_i_ne_-C_he_c_k_E_x_te_n_d_ed_L_09_O_u_t _L_en_g_th ___ --' Bits 0-5, 7, 8
Bits 14-15
Bits 16-18
Bits 20-31,46,47
Bits 6, 9-13,19,26,32-45 Subclass Time of interruption occurrence Storage errors Validity indicators
Not assigned, stored as zeros
Machine Check Interruption-Code Format
178 System/370 Principles of Operation
63

imply storage logical validity, or that the fields stored
as a result of the machine-check interruption are
valid. The presence and extent of the system re­
covery capability depend on the model.
Timer Damage (ID): Bit 3, when one, indicates
that damage has occurred to the interval timer or to
location 80. Timing Facility Damage (CD): Bit 4, when one,
indicates that damage has occurred to either the
time-of-day clock, the CPU timer, or the clock com­
parator. The timing-facility-damage machine-check
condition is set whenever any of the following oc­
curs:
1. The time-of-day clock enters the not­
operational state.
2. The time-of -day clock enters the error state.
3. The time-of-day clock is not in the error state,
and the STORE CLOCK instruction encoun­
ters an error which results in setting condition
code 2. This condition also sets instruction
processing damage.
4.
The CPU timer is in error, and the CPU is ena­
bled for CPU-timer interruptions. On some
models, this condition may be recognized even
when the CPU is not enabled for CPU-timer interruptions.
5. The CPU timer is in error, and STORE CPU TIMER is executed. This condition also sets
instruction processing damage.
6. The clock comparator is in error, and the CPU is enabled for clock-comparator interruptions. On some models, this condition may be recog­
nized even when the CPU is not enabled for
clock-comparator interruptions.
7. The clock comparator is in error, and STORE CLOCK COMPARATOR is executed. This
condition also sets instruction processing dam­
age. External Damage (ED): Bit 5, when one, indicates
that damage has occurred to a channel, channel con­
troller, switching unit, or other unit external to the CPU, or to a storage unit during operations not di­
rectly associated with the CPU. Channel-detected
malfunctions are reported as external damage only
when the channel is unable to report the malfunction
by using the 110 interruption. Depending on the
model and on the type and extent of the error, an
external damage condition may be indicated as sys­
tem damage instead of external damage.
Degradation (DG): Bit 7, when one, indicates that
continuous degradation of system performance,
more serious than that indicated by system recovery,
has occurred. Degradation may be reported when
system-recovery conditions exceed a machine pre­
established threshold or when unit deletion has oc­
curred. The presence and extent of the degradation­
report capability depends on the model.
Warning (W): Bit 8, when one, indicates that dam­
age is imminent in some part of the system (for ex­
ample, that power is about to fail, or that a loss of
cooling is occurring). Whether warning conditions
are recognized depends on the model.
Time of Interruption Occurrence
Bits 14 and 15 of the machine-check interruption
code indicate when the interruption occurred in rela­
tion to the error.
Backed Up (B): Bit 14, when one, indicates that
the point of interruption is at a hardware checkpoint
before the point of error. This bit is meaningful only
when instruction processing damage is also set to
one. The presence and extent of the capability to
indicate a backed-up condition depends on the mod­
el.
Programming Note
The backed-up situation is reported as instruction­
processing damage rather than system recovery be­
cause the malfunction has not been circumvented
and damage would have occurred if instruction pro­ cessing had continued.
Delayed (D): Bit 15, when one, indicates that some
or all of the machine-check conditions were delayed
in being reported because the CPU was disabled for
that type of interruption at the time the error was
detected.
Storage Error Type
Bits 16-18 of the machine-check interruption code
are used to indicate invalid CBC or near-valid CBC
detected in main storage or invalid CBC in a key in
storage. The failing-storage address field, when indi­
cated as valid, identifies an address within the stor­
age checking block or within the 2,048-byte block
associated with the key in storage. The portion of
the system affected by an invalid CBC is indicated in
the subclass field of the machine-check interruption
code. I/O-detected storage errors, when indicated as 110 interruptions, may not result in a machine-check
interruption or may be reported as system recovery.
CBC errors in storage or in the key in storage that
Machine-Check Handling 179