Input I O,'tput Extended Logout Control (lL): Bit 2
of contrOiI register 14, when one, permits channel
logout into the 110 extended logout area as part of
an 110 interruption. When the 110 extended logout
mask is zero, 1/0 extended logouts cannot occur.
This bit is initialized to zero.
Asynchronous Machine-Check Extended Logout
Control (AL): Bit 8 of control register 14, in con­
junction with PSW bit 13, controls asynchronous
change of the machine-check extended logout area.
When this bit and PSW bit 13 are both ones, the
machine may change the machine-check extended
logout area at any time. This bit is initialized to zero.
Asynchronous Fixed Logout Control (FL): Bit 9 of
control register 14, when one, permits the fixed log­
out area to be changed at any time. When this bit is
zero, the fixed logout area may be changed only
during a machine-check interruption or during an 110 interruption. This bit is initialized to zero.
Programming Notes
The maximum logout information is obtained by
setting both the synchronous and asynchronous
machine-check extended logout control bits to ones.
Both of these bits must be zeros to prevent any
changes to the machine-check extended logout area.
When asynchronous machine-check extended logout
is allowed, use of the machine-check extended log­
out area may produce unpredictable results.
When the asynchronous fixed logout control bit is
one, program use of the fixed logout area should be
restricted to the fetching of data from this are,a.
Store operations or channel programs reading into
the fixed logout area may cause machine checks or
undetected errors if the store occurs during CPU retry. Note that this is an exception to the rule
that programming errors do not cause machine­
check indications.
Machine··Check Subclass Masks
Bits 4-7 of control register 14, in conjunction with PSW bit 13, control various machine-check subclass
conditions. When PSW bit 13 is one and the subclass
mask is OIne, the associated condition initiates a
machine-,check interruption. If the subclass mask is
zero, the associated condition does not initiate an
182 System/370 Principles of Operation
interruption, but the condition may be presented
with another condition which initiates the interrup­
tion. All conditions presented are then cleared. Recovery Report Mask (RM): Bit 4 of control reg­
ister 14 controls recovery-interruption conditions.
This bit is initialized to zero.
Degradation Report Mask (DM): Bit 5 of control
register 14 controls degradation-interruption condi­
tions. This bit is initialized to zero.
External Damage Report Mask (EM): Bit 6 of con­
trol register 14 controls the following machine-check­
interruption conditions: timer damage, timing facility
damage, and external damage. This bit is initialized
to one.
Warning Mask (WM): Bit 7 of control register 14
controls all warning conditions. This bit is initialized
to zero.
Control Register 15
o 8
Machine-Check Extended Logout
Address
29 31
Bits 8-28 of control register 15, with three low-order
zeros appended, specify the starting location of the
machine-check extended logout area. The contents
of control register 15 are initialized by setting bit 22
to one and ali other bits to zeros, which specifies a
starting address of 512 (decimal). The machine­
check extended logout address is a real address.
When a model provides machine-check extended
logout, control register 15 is implemented.
Programming Note
The availability and extent of the machine-check
extended logout area differs among models and, for
any particular model, may depend on the features or
engineering changes installed. In order to provide for
such variations, the program should determine the
extent of the logout by means of STORE CPU ID
whenever a storage area for the extended logout is to
be assigned. A length of zero in the MCEL field
indicates that no MCEL is provided.
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Summary of Machine-Check Masking
Subclass Condition SD System Damage
PD Instruction Processing Damage
TD Timer Damage
CD Timing Facilities Damage SR System Recovery
ED External Damage
DG Degradation
W Warning
Explanati on:
P Indication held pending.
Subclass Mask
EM
EM
RM
EM
DM
WM
Action When CPU Disabled for Condition
Check-Stop Control = 0 P*
P*
P
P
Y
P
P
P
Check-Stop Control = 1
Check stop
Check stop
P
P
Y
P
P
P
Y Indication may be held pending or may be discarded.
* In this situation, the system integrity may have been lost, and the system cannot be considered dependable.
Machine-Check Condition Masking PSW Bit 13
o
AFL Control
SMCEL Control
CR 14 Bit 1
X
o
o
AMCEL Control
CR14Bit8
X
o
o
Machine-Check Extended Logout Action
No MCEL
No MCEL
MCEL may occur only during machine-check interruption.
1
MCEL may occur at any time.
2
MCEL may occur at any time.
Fixed Logout Action
o CPU portion of fixed logout area may be changed only during machine-check interruption.
1
CPU portion 'Of fixed logout area may be changed at any time.
Explanation:
X Indicates the same action occurs whether the bit is zero or one.
Logout prior to instruction retry is not permissible in this state even though recovery reports are enabled.
2 In some models the AMCEL mask bit is ignored, and no logout occurs in this state.
Machine-Check Logout Control
Control Register 14 State of Bit on Initial Bit Description Bit Position Program Reset CS Check-stop control 0 SL Synchronous MCEL mask 1 IL IOEL control 2 0 RM Recovery report mask 4 0 DM Degradation report mask 5 0 EM External damage report mask 6 1
WM Warning mask 7 0 AL Asynchronous MCEL control 8 0 FL Asynchronous fixed logout control 9 0 Machine-Check Control Register Bits
Machine-Check Handling 183
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