Direct Control
The direct-control feature provides two instructions,
READ DIRECT and WRITE DIRECT, and an
external-signal facility, consisting of six external
interruption lines. This feature operates indepen
dently of the facilities for performingI/O operations.
The read and write instructions provide for the
transfer of a single byte of information, normally for
controlling or synchronizing purposes, between two
cable-connected processing units or a cable
connected processing unit and external devices. Each
of the six external lines, when pulsed, sets up the
conditions for an external interruption.
Note:Some models provide the external-signal facili
ty as a separate feature (without the READ DIRECT
and WRITE DIRECT instructions).
For a detailed description of direct control, see
theSystem/360 and System/370 Direct Control
and External Interruption Features--Original
Equipment Manufacturers' Information, GA22-
6845.
Time-of-Day Clock
The time-of-day clock provides a consistent measure
of elapsed time suitable for the indication of date
and time. The cycle of the clock is approximately
143 years.
In an installation with more than oneCPU, de
pending on the model, eachCPU may have a sepa
rate time-of -day clock, or more than oneCPU may
share a dock. In all cases, eachCPU accesses a sin
gle clock.
Format
The time-of -day clock is a binary counter with a
format as shown in the following illustration. The bit
positions of the clock are numbered0 to 63, corre
sponding to the bit positions of an unsigned fixed
point number of double precision. Time is measured
by incrementing the value of the clock, following the
rules for unsigned fixed-point arithmetic.c. ___ o 31 32 52
In the basic form, the clock is incremented by
adding a one in bit position 51 every microsecond.
46System/370 Principles of Operation
63
In models having a higher or lower resolution, a dif
ferent bit position is incremented at such a frequen
cy that the rate of advancement of the clock is the
same as if a one were added in bit position 51 every
microsecond. The resolution of the time-of -day
clock is such that the incrementing rate is compara
ble to the instruction execution rate of the model.
When more than one time-of -day clock exists in a
configured system, the stepping rates are synchro
nized such that all time-of-day clocks in the configu
ration are incremented at the exact same rate.
When incrementing of the clock causes a carry to
be propagated out of bit position0, the carry is ig
nored, and counting continues from zero on. The
program is not alerted, and no interruption condition
is generated as a result of the overflow.
The operation of the clock is not affected or in
hibited by any normal activity or event in the sys
tem. The clock runs when theCPU is in the wait or
stopped state, or in the instruction-step, single-cycle,
or test mode, and its operation is not affected byCPU, initial-CPU, program, initial-program, or
system-clear resets or by theIPL procedure. De
pending on the implementation, the clock mayor
may not run with theCPU power off.
States
The following states are distinguished for the time
of -day clock: set, not set, stopped, error, and not
operational. The state determines the condition code
set bySTORE CLOCK. The clock is said to be run
ning when it is in either the set or not-set state.
The clock is in the not-operational state when its
power is down or when it is disabled for mainte
nance. It depends on the model if the clock can be
placed in this state.
When the power for the clock is turned on, the_
value of the clock is set to zero, and the clock enters
the not-set state. With the clock in this state,STORE CLOCK causes condition code 1 to be set.
The clock enters the stopped state whenSET CLOCK causes the clock's contents to be set, that
is, whenSET CLOCK is executed without encoun
tering any exceptions and with the TOD-clock
switch in the enable-set position. The clock can be
placed in the stopped state from the set, not-set, and
error states. The clock is not incremented while in
the stopped state. When the clock is in the stopped
state,STORE CLOCK causes the value of the
stopped clock to be stored and condition code 3 to be
set. This is distinguished from the not-operational
state, where condition code 3is set and a value of
zero is stored.
The clock enters the set state only from the
stopped state. This is under control of the time-of-day
The direct-control feature provides two instructions,
READ DIRECT and WRITE DIRECT, and an
external-signal facility, consisting of six external
interruption lines. This feature operates indepen
dently of the facilities for performing
The read and write instructions provide for the
transfer of a single byte of information, normally for
controlling or synchronizing purposes, between two
cable-connected processing units or a cable
connected processing unit and external devices. Each
of the six external lines, when pulsed, sets up the
conditions for an external interruption.
Note:
ty as a separate feature (without the READ DIRECT
and WRITE DIRECT instructions).
For a detailed description of direct control, see
the
and External Interruption Features--Original
Equipment Manufacturers' Information, GA22-
6845.
Time-of-Day Clock
The time-of-day clock provides a consistent measure
of elapsed time suitable for the indication of date
and time. The cycle of the clock is approximately
143 years.
In an installation with more than one
pending on the model, each
rate time-of -day clock, or more than one
share a dock. In all cases, each
gle clock.
Format
The time-of -day clock is a binary counter with a
format as shown in the following illustration. The bit
positions of the clock are numbered
sponding to the bit positions of an unsigned fixed
point number of double precision. Time is measured
by incrementing the value of the clock, following the
rules for unsigned fixed-point arithmetic.
In the basic form, the clock is incremented by
adding a one in bit position 51 every microsecond.
46
63
In models having a higher or lower resolution, a dif
ferent bit position is incremented at such a frequen
cy that the rate of advancement of the clock is the
same as if a one were added in bit position 51 every
microsecond. The resolution of the time-of -day
clock is such that the incrementing rate is compara
ble to the instruction execution rate of the model.
When more than one time-of -day clock exists in a
configured system, the stepping rates are synchro
nized such that all time-of-day clocks in the configu
ration are incremented at the exact same rate.
When incrementing of the clock causes a carry to
be propagated out of bit position
nored, and counting continues from zero on. The
program is not alerted, and no interruption condition
is generated as a result of the overflow.
The operation of the clock is not affected or in
hibited by any normal activity or event in the sys
tem. The clock runs when the
stopped state, or in the instruction-step, single-cycle,
or test mode, and its operation is not affected by
system-clear resets or by the
pending on the implementation, the clock mayor
may not run with the
States
The following states are distinguished for the time
of -day clock: set, not set, stopped, error, and not
operational. The state determines the condition code
set by
ning when it is in either the set or not-set state.
The clock is in the not-operational state when its
power is down or when it is disabled for mainte
nance. It depends on the model if the clock can be
placed in this state.
When the power for the clock is turned on, the_
value of the clock is set to zero, and the clock enters
the not-set state. With the clock in this state,
The clock enters the stopped state when
is, when
tering any exceptions and with the TOD-clock
switch in the enable-set position. The clock can be
placed in the stopped state from the set, not-set, and
error states. The clock is not incremented while in
the stopped state. When the clock is in the stopped
state,
stopped clock to be stored and condition code 3 to be
set. This is distinguished from the not-operational
state, where condition code 3
zero is stored.
The clock enters the set state only from the
stopped state. This is under control of the time-of-day