zeros :appended, form a 24-bit real address that des
ignates the beginning of the page table.
segment associated with the segment-table entry is
available. When bit position 31 contains a zero, ad
dress
table. When the bit is a one, a segment-translation
exception is recognized, and the unit of operation is
the segment-table entry depends on the model. Nor
mally a translation-specification exception is recog
nized and the unit of operation is suppressed when
these bits are not zeros; however, on some models
the contents of these bit positions may be ignored.
The entry fetched from the page table indicates the
availability of the page and contains the high-order
bits of the real address. The format of the page-table
entry depends on page size, as follows:
The fields in the page-table entry are allocated as
follows:
Page Address: Bits 0-11 or bits 0-12, depending on
the page size, provide the leftmost 12 or 13 bits of a
24-bit real storage address. When the page address
and the contents of the byte-index field of the logi
cal address are concatenated, with the page address
forming the high-order part, the real storage address
is obtained.
Page'-Invalid Bit: Bit 12 or 13, depending on the
page size, controls whether the page associated with
the page-table entry is available. When the bit is
zero" address translation proceeds using the table
entry. When the bit is one, a page-translation excep
tion is recognized, and the unit of operation is nulli
fied.
Except for the rightmost bit position of the entry,
the bit positions to the right of the page-invalid bit
must contain zeros; otherwise, a translation-
specification exception is recognized as part of the
execution of an instruction using that entry for ad
dress translation, and the unit of operation is sup
pressed.
Programming Notes
A segment-table or page-table length code in excess
of the maximum usable length code is valid. For
example, the length code is valid even if the end of
the table falls outside the available main storage or if
part of the table is not addressable by the logical
address.
The low-order bit position of a page-table entry is
unassigned and is not checked for zero; thus, it is
available for programming use.
Translation
Types of Translation
Two types of translation of main-storage addresses
are distinguished--implicit and explicit. An explicit
translation is one that is invoked for the translation
of the operand address of
struction addresses and of addresses of main-storage
operands for all other instructions is referred to as
implicit translation.
Translation Process
Translation is performed by means of a segment
table and a page table, both of which reside in main
storage. It is controlled by the translation-mode bit
in the
The segment-index portion of the logical address
is used to select an entry from the segment table, the
starting address and length of which are specified by
the contents of control register 1. This entry desig
nates the page table to be used. The page-index por
tion of the logical address is used to select an entry
from the page table. This entry, the format of which
depends on the size of the page, contains the high
order bits of the real address that corresponds to the
logical address. The byte-index field of the logical
address is used unchanged for the low-order bit posi
tions of the real address.
In order to avoid the delay associated with refer
ences to translation tables in main storage, the in
formation fetched from the tables normally is placed
also in a special buffer, the translation-lookaside
buffer (TLB), and subsequent translations involving
the same table entries may be performed using the
information recorded in the TLB.