Page-Table Address: Bits 8-28, with three low-order
zeros :appended, form a 24-bit real address that des­
ignates the beginning of the page table. Bit: Bit 31 controls whether the
segment associated with the segment-table entry is
available. When bit position 31 contains a zero, ad­
dress translation proceeds using the designated page
table. When the bit is a one, a segment-translation
exception is recognized, and the unit of operation is nullified. The handling of bit positions 4-7 and 29-30 of
the segment-table entry depends on the model. Nor­
mally a translation-specification exception is recog­
nized and the unit of operation is suppressed when
these bits are not zeros; however, on some models
the contents of these bit positions may be ignored. Table Entries
The entry fetched from the page table indicates the
availability of the page and contains the high-order
bits of the real address. The format of the page-table
entry depends on page size, as follows: Page-table entry with 4K-byte pages: Add,." o Page··table entry with 2K-byte pages: L Page Add,." o
The fields in the page-table entry are allocated as
follows:
Page Address: Bits 0-11 or bits 0-12, depending on
the page size, provide the leftmost 12 or 13 bits of a
24-bit real storage address. When the page address
and the contents of the byte-index field of the logi­
cal address are concatenated, with the page address
forming the high-order part, the real storage address
is obtained.
Page'-Invalid Bit: Bit 12 or 13, depending on the
page size, controls whether the page associated with
the page-table entry is available. When the bit is
zero" address translation proceeds using the table
entry. When the bit is one, a page-translation excep­
tion is recognized, and the unit of operation is nulli­
fied.
Except for the rightmost bit position of the entry,
the bit positions to the right of the page-invalid bit
must contain zeros; otherwise, a translation- 60 System/370 Principles of Operation
specification exception is recognized as part of the
execution of an instruction using that entry for ad­
dress translation, and the unit of operation is sup­
pressed.
Programming Notes
A segment-table or page-table length code in excess
of the maximum usable length code is valid. For
example, the length code is valid even if the end of
the table falls outside the available main storage or if
part of the table is not addressable by the logical
address.
The low-order bit position of a page-table entry is
unassigned and is not checked for zero; thus, it is
available for programming use.
Translation
Types of Translation
Two types of translation of main-storage addresses
are distinguished--implicit and explicit. An explicit
translation is one that is invoked for the translation
of the operand address of LOAD REAL ADDRESS. The procedure invoked for the translation of all in­
struction addresses and of addresses of main-storage
operands for all other instructions is referred to as
implicit translation.
Translation Process
Translation is performed by means of a segment
table and a page table, both of which reside in main
storage. It is controlled by the translation-mode bit
in the PSW and by a set of bits in control registers 0 and 1.
The segment-index portion of the logical address
is used to select an entry from the segment table, the
starting address and length of which are specified by
the contents of control register 1. This entry desig­
nates the page table to be used. The page-index por­
tion of the logical address is used to select an entry
from the page table. This entry, the format of which
depends on the size of the page, contains the high­
order bits of the real address that corresponds to the
logical address. The byte-index field of the logical
address is used unchanged for the low-order bit posi­
tions of the real address.
In order to avoid the delay associated with refer­
ences to translation tables in main storage, the in­
formation fetched from the tables normally is placed
also in a special buffer, the translation-lookaside
buffer (TLB), and subsequent translations involving
the same table entries may be performed using the
information recorded in the TLB.
Control Register 1 Logical Address I I I I Segment Page I Byte Index J Ingex Ini ex - .-l J L CD I CD Segment Table * + + , Page Table*
( ) I CD ® J. CD __ 0 I ". .- -l CD @ l L..o..- I I Translation- Lookaside
Buffer (TLB) Real Address
* In Main Storage CD Information, which may include portions of the logical address and the segment·table address,
is used to search the TLB. ® If match exists, address from TLB is used in forming the real address. 0) If no match exists, table entries in main storage are fetched to translate the address. Resulting value, in conjunction with search information, is used to form an entry in the TLB.
Translation Process The translation process, including the effect of
the TLB, is shown graphically in the figure "Translation Process." Inspection of Control Register 0
The interpretation of the logical address for transla­
tion purposes is controlled by the segment size and
page size, which are specified by the contents of bit
positions 8-12 of control register O. If bit positions
8-9 or 11-12 contain an invalid code or if bit 10 is
one, a translation-specification exception is recog­
nized, and the operation is suppressed.
Segment Table Lookup
The segment-index portion of the logical address is
used to select a segment-table entry that designates
the page table to be used in arriving at the real ad­
dress. The address of the segment-table entry is ob­
tained by appending six low-order zeros to the con­
tents of bit positions 8-25 of control register 1 and
adding the segment index to this value, with the low­
order bit position of the segment index aligned with
bit position 29 of the segment-table address.
As part of the segment-table lookup process, the
segment index is compared against the segment-table
length, bits 0-7 of control register 1, to establish
whether the addressed entry is within the table.
With 1M-byte segments, entries for all addressable
segments are contained in a table of minimum length
(length code of 0). With 64K-byte segments, four
high-order zeros are appended to the contents of bit
positions 8-11 of the logical address, and this ex­
tended value is compared against the eight-bit
segment-table length. If the value in the segment­
table-length field is less than the value in the corre­
sponding bit positions of the logical address, a
segment-translation exception is recognized, and the
unit of operation is nullified.
If the storage address generated for fetching the
segment-table entry refers to a location outside the
main storage of the installed system, an addressing
exception is recognized, and the unit of operation is
suppressed.
Bit 31 of the entry fetched from the segment ta­
ble specifies whether the corresponding segment is
available. This bit is inspected, and, if it is one, a
segment-translation exception is recognized, with the
unit of operation nullified. Handling of bit positions
4-7 and 29-30 of the segment-table entry depends
on the model: normally a translation-specification
exception is indicated and the unit of operation is
suppressed when they do not contain zeros; howev­
er, on some models they may be ignored.
When no exceptions are recognized in the process
of segment-table lookup, the entry fetched from the
segment table designates the length and beginning of
the corresponding page table.
Page Table Lookup
The page-index portion of the logical address, in
conjunction with the page-table address derived
from the segment-table entry, is used to select an
entry from the page table. The page-table-entry ad-
Dynamic Address Translation 61
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