Mask Bits PSW Mask in Control Source Interruption
Bits Registers
Execution of Instruction
Identification Code
BC EC Register Bit ILC Set Identified by Old PSW ----
Machine check (old PSW 48, new PSW 112)
Exigent condition mmmmmmmm mmmmmmmm
1
13 13 x terminated or nullified
7
Repressible condo mmmmmmmm mmmmmmmm
1
13 13 14 4-7 x unaffected
7
Supervisor call (old PSW 32, new PSW 96) I nstruction bits 00000000 rrrrrrrr 1,2 completed
Program (old PSW 40, new PSW 104) Operation 00000000 nOOOOO01 1,2,3 suppressed
Privileged oper. 00000000 nooOO010 1,2 suppressed
Execute 00000000 nOOOO011 2 suppressed
Protection 00000000 riOOO0100 0,1,2,3 suppressed or terminated
Addressing 00000000 nOOO0101 0,1,2,3 suppressed or terminated
Specification 00000000 nOOO0110 0,1,2,3 suppressed or completed
Data 00000000 nOOOOlll 2,3 suppressed or terminated
Fixed-pt. overflow 00000000 nOO01000 36 20 1,2 completed
Fixed-point divide 00000000 nOO01001 1,2 suppressed or completed
Deci mal overflow 00000000 nOO01010 37 21 2,3 completed
Decimal divide 00000000 nOO01011 2,3 suppressed
Exponent overflow 00000000 nOO01100 1,2 completed
Exponent underflow 00000000 nOO01101 38 , 22 1,2 completed SignificancE! 00000000 nOOOll10 39 23 1,2 completed
Floating-pt. divide 00000000 nOO01111 1,2 suppressed
Segment transl. 00000000 n0010000 1,2,3 nullified
Page translation 00000000 n0010001 1,2,3 nullified
Translation spec 00000000 n0010010 1,2,3 suppressed
Special opelration 00000000 n00100ll 0 2 suppressed
Monitor event 00000000 nl000000 8 16+ 2 completed
Program evont 00000000 leOeeeee
2
9 0-3 0,1,2,3 completed
3
External (old PSW 24, new PSW 88) Interval timer 00000000 lnnnnnnn 7 7 0 24 x unaffected I Interrupt kE!y 00000000 nlnnnnnn 7 7 0 25 x unaffected
External signal 2 00000000 nn1nnnnn 7 7 0 26 x unaffected
External signal 3 00000000 nnnlnnnn 7 7 0 26 x unaffected
External signal 4 00000000 nnnn1nnn 7 7 0 26 x unaffected
External signal 5 00000000 nnnnn1nn 7 7 0 26 x uriaffected
External signal 6 00000000 nnnnnn1n 7 7 0 26 x unaffected
External signal 7 00000000 nnnnnnn1 7 7 0 26 x unaffected
Malfunction alert 00010010 00000000 7 7 0 16 x unaffected
Emergency signal 00010010 00000001 7 7 0 17 x unaffected
External call 00010010 00000010 7 7 0 18 x unaffected TOO clock sync chk 000.10000 00000011 7 7 0 19 x unaffected
Clock comparator 00010000 00000100 7 7 0 20 x unaffected
CPU timer 00010000 00000101 7 7 0 21 x unaffected Input/Output (old PSW 56, new PSW 120) Channel 0 00000000 dddddddd
4 0 6 2 0
5
x unaffected
Channell 00000001 dddddddd
4
1 6 2 1
5
x unaffected
Channel 2 00000010 dddddddd
4
2 6 2 2
5
x unaffected
Channel 3 00000011 dddddddd
4
3 6 2 3
5
x unaffected
Channel 4 00000100 dddddddd
4
4 6 2 4
5
x unaffected
Channel 5 00000101 dddddddd
4
5 6 2 55 x unaffected
Channels 6 c31 on cccccccc dddddddd
4
6 6 2 6+ x unaffected
Restart (old PSW 8, new PSW 0) Restart key 00000000 00000000
6
x unaffected
Interruption Action
72 System/370 Principles of Operation
Explanation:
A machine-check interruption code of 64 bits is stored at
locations 232-239.
2 When the interruption code indicates a program event, an I LC
of zero may be stored only when the code formed by bits
12-15 of the interruption code has a nonzero value.
3 The unit of operation is completed, unless a program exception
concurrently indicated has caused the unit of operation to be nullified, suppressed, or terminated.
4 In the EC mode, the I/O address is stored at locations 186-187.
5 For channels 0-5, channel masks in control register 2 have no
effect in BC mode.
6 Bits 16-31 in the old PSW in BC mode are set to zeros. No
interruption code is provided in EC mode.
7 For any machine-check interruption condition, either exigent
or repressible, the effect of this condition is identified by the
validity bits in the machine-check interruption code. The
instruction has been nullified or unaffected only if the
associated validity bits are set to ones.
Interruption Action (Continued)
other than an odd instruction address, and, concur­
rently, the LOAD PSW or SUPERVISOR CALL
instruction causes a program event, the ILC is 0, as called for in the specification exception.
ILC on Instruction Fetch Exceptions
When a program interruption occurs because of an
exception that prohibits access to the instruction, the
instruction-length code cannot be set on the basis of
the first two bits of the instruction. As far as the
significance of the ILC for this case is concerned,
the following two situations are distinguished:
1. When an odd instruction address causes a spec­
ification exception to be recognized or when a
protection, addressing, or translation­
specification exception is encountered on
fetching an instruction, the instruction-length
code is 1, 2, or 3, indicating the number of
halfwords by which the instruction address has
been incremented. When the instruction ad­
dress in the old PSW is reduced by the number
of halfword locations indicated by the
instruction-length code, the address originally
appearing in the PSW is obtained. It is unpre­
dictable whether the code is 1, 2, or 3.
2. When a segment-translation or page-translation
exception is recognized on the access to an
instruction, the ILC is 1, 2, or 3, with the indi­
cation being unpredictable. In this case the op­
eration is nullified, and the instruction address
is not incremented.
The ILC is not necessarily related to the first two
bits of the instruction when the first halfword of an
instruction can be fetched but an access exception is
recognized on fetching the second or third halfword.
+ Plus the following bits in the control register.
* In BC mode, program-event recording is disabled. c Channel address bits.
d Device address bits.
e A possible nonzero code indicating another program
interruption condition.
m Bits of model-dependent code.
n Possible bit-significant indication of other concurrent
interruption conditions.
r Bits of the I field of SUPERVISOR CALL.
x Unpredictable in BC mode; not stored in EC mode.
When any exceptions are encountered on fetching
the subject instruction of EXECUTE, the ILC is 2.
Programming Notes
A nonzero instruction-length code for a program
interruption indicates the number of halfword loca­
tions by which the instruction address in the old
PSW must be reduced to obtain the address of the
last instruction executed, unless one of the following
situations exists:
1. The interruption is caused by a segment­
translation or page-translation exception.
2. An interruption for a program event occurs
before the completion of the execution of an
interruptible instruction.
3. The interruption is caused by a program event
due to a branch instruction, LOAD PSW, or SUPERVISOR CALL.
4. The interruption is caused by an access excep­
tion encountered in fetching an instruction,
and the instruction address has been intro­
duced into the PSW by a means other than
sequential operation (by a branch instruction,
LOAD PSW, or an interruption).
S. The interruption is caused by a specification
exception because of an odd instruction ad­
dress.
6. The interruption is caused by a specification or
access exception encountered in fetching an
instruction, and changes have been made or
may have been made to the parameters that
control the relation between the logical and
real instruction address (turning the translation
mode on or off without introducing an entire
new PSW, changing the translation-control
Interruptions 73
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