Explanation:
A machine-check interruption code of 64 bits is stored at
locations 232-239.
2 When the interruption code indicates a program event, an I LC
of zero may be stored only when the code formed by bits
12-15 of the interruption code has a nonzero value.
3 The unit of operation is completed, unless a program exception
concurrently indicated has caused the unit of operation to be nullified, suppressed, or terminated.
4 In the EC mode, the I/O address is stored at locations 186-187.
5 For channels 0-5, channel masks in control register 2 have no
effect in BC mode.
6 Bits 16-31 in the old PSW in BC mode are set to zeros. No
interruption code is provided in EC mode.
7 For any machine-check interruption condition, either exigent
or repressible, the effect of this condition is identified by the
validity bits in the machine-check interruption code. The
instruction has been nullified or unaffected only if the
associated validity bits are set to ones.
Interruption Action (Continued)
other than an odd instruction address, and, concur­
rently, the LOAD PSW or SUPERVISOR CALL
instruction causes a program event, the ILC is 0, as called for in the specification exception.
ILC on Instruction Fetch Exceptions
When a program interruption occurs because of an
exception that prohibits access to the instruction, the
instruction-length code cannot be set on the basis of
the first two bits of the instruction. As far as the
significance of the ILC for this case is concerned,
the following two situations are distinguished:
1. When an odd instruction address causes a spec­
ification exception to be recognized or when a
protection, addressing, or translation­
specification exception is encountered on
fetching an instruction, the instruction-length
code is 1, 2, or 3, indicating the number of
halfwords by which the instruction address has
been incremented. When the instruction ad­
dress in the old PSW is reduced by the number
of halfword locations indicated by the
instruction-length code, the address originally
appearing in the PSW is obtained. It is unpre­
dictable whether the code is 1, 2, or 3.
2. When a segment-translation or page-translation
exception is recognized on the access to an
instruction, the ILC is 1, 2, or 3, with the indi­
cation being unpredictable. In this case the op­
eration is nullified, and the instruction address
is not incremented.
The ILC is not necessarily related to the first two
bits of the instruction when the first halfword of an
instruction can be fetched but an access exception is
recognized on fetching the second or third halfword.
+ Plus the following bits in the control register.
* In BC mode, program-event recording is disabled. c Channel address bits.
d Device address bits.
e A possible nonzero code indicating another program
interruption condition.
m Bits of model-dependent code.
n Possible bit-significant indication of other concurrent
interruption conditions.
r Bits of the I field of SUPERVISOR CALL.
x Unpredictable in BC mode; not stored in EC mode.
When any exceptions are encountered on fetching
the subject instruction of EXECUTE, the ILC is 2.
Programming Notes
A nonzero instruction-length code for a program
interruption indicates the number of halfword loca­
tions by which the instruction address in the old
PSW must be reduced to obtain the address of the
last instruction executed, unless one of the following
situations exists:
1. The interruption is caused by a segment­
translation or page-translation exception.
2. An interruption for a program event occurs
before the completion of the execution of an
interruptible instruction.
3. The interruption is caused by a program event
due to a branch instruction, LOAD PSW, or SUPERVISOR CALL.
4. The interruption is caused by an access excep­
tion encountered in fetching an instruction,
and the instruction address has been intro­
duced into the PSW by a means other than
sequential operation (by a branch instruction,
LOAD PSW, or an interruption).
S. The interruption is caused by a specification
exception because of an odd instruction ad­
dress.
6. The interruption is caused by a specification or
access exception encountered in fetching an
instruction, and changes have been made or
may have been made to the parameters that
control the relation between the logical and
real instruction address (turning the translation
mode on or off without introducing an entire
new PSW, changing the translation-control
Interruptions 73
parameters in control registers 0 and 1, intro­
ducing invalid values in bit positions 0-7 of an
Ee PSW). For situations 1 and 2, the operation is nullified,
and the instruction designated by the instruction
address is the same as the last one executed. These
two are the only ca'ses where the instruction address
in the old PSW identifies the instruction causing the
exception.
For situations 3, 4, and 5, the instruction address
in the prlOgram old PSW has been replaced and can­
not be calculated using the one appearing in the PSW. For situation 6, the logical instruction address in
the PSW has not been replaced, but the correspond­
ing real address after the change is different.
When bit 8 (program event) in the interruption
code is on, the PER address at locations 153-155
identifies the location of the instruction causing the
interruption, and the instruction-length code OLC) is redundant. Similarly, the ILC is redundant when
the operation is nullified, since in this case the ILC
can be derived from the operation code of the in­
struction identified by the old PSW. Point 01 Interr.llption An interruption is permitted between that is, an interruption can occur after the perform­
ance of one operation and before the start of a sub­
sequent operation. The entire execution of an in­
struction is an operation.
For the two instructions MOVE LONG and COMPAlRE LOGICAL LONG, referred to as inter­
ruptible instructions, an interruption is permitted
after a partial execution of the instruction. The exe­
cution of an interruptible instruction is considered to
consist of a number of units of operation, and an
interruption is permitted between units of operation.
The amount of data processed in a unit of operation
depends on the particular instruction and may de­
pend on the model and on the particular condition
that causes the execution of the instruction to be
interrupted.
Whenever discussion in this publication pertains
to points IOf interruptibility that include those occur­
ring within the execution of an interruptible instruc­
tion, the term "unit of operation" is used. This use
of the term considers that the entire execution of the
noninterrnptible instruction consists, in effect, of
one unit of operation.
Programming Note
Any interruption, other than supervisor call and
some program interruptions, can occur after a partial
execution of an interruptible instruction. In pa:rticu-
74 System/370 Principles of Operation lar, interruptions for I/O, external, and machine­
check conditions and for program access exceptions
can occur between units of operation.
Instruction Execution
Types of Ending
Instruction execution is said to end in one of four
ways--completion, nullification, suppression, and
termination.
When the execution of an instruction is complet­
ed, results are provided as called for in the definition
of the instruction. When an interruption occurs after
the completion of the execution of an instruction,
the instruction address in the old PSW designates the
next instruction to be executed" When the execution of an instruction is sup­
pressed, the instruction is executed as if it specified "no operation." The contents of any result fields,
including the condition code, are not changed. The
instruction address in the old PSW on an interrup­
tion after suppression designates the next sequential
instruction.
Nullification is the same as suppression, except
that when an interruption occurs after the execution
of the instruction has been nullified, the instruction
address in the old PSW designates the instruction
whose execution was nullified instead of the next
sequential instruction.
When the execution of an instruction is terminat­
ed, the contents of any fields due to be changed by
the instruction are unpredictable. The operation may
have replaced all, part, or none of the contents of
the designated result fields and may have changed
the condition code if such change was called for by
the instruction. Unless the interruption is caused by
a machine-check condition, the validity of the in­
struction address in the PSW, the interruption code,
and the instruction-length code are not affected; and
the state or the operation of the system has not been
affected in any other way. The instruction address in
the old PSW on an interruption after termination
designates the next sequential instruction.
Execution of Interruptible Instructions
The execution of an interruptible instruction is com­
pleted when all units of operation associated with
that instruction are completed. When an interruption
occurs after completion, nullification, or suppression
of a unit of operation, all prior units of operation
have been completed. On completion of a unit of operation other than
the last one and on nullification of any unit of opera­
tion, the instruction address in the old PSW desig­
nates the interrupted instruction, and the operand
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