Explanation:
A machine-check interruption code of 64 bits is stored at
locations 232-239.
2 When the interruption code indicates a program event, anI LC
of zero may be stored only when the code formed by bits
12-15 of the interruption code has a nonzero value.
3 The unit of operation is completed, unless a program exception
concurrently indicated has caused the unit of operation to benullified, suppressed, or terminated.
4In the EC mode, the I/O address is stored at locations 186-187.
5 For channels0-5, channel masks in control register 2 have no
effect in BC mode.
6 Bits 16-31 in theold PSW in BC mode are set to zeros. No
interruption code is provided in EC mode.
7 For any machine-check interruption condition, either exigent
or repressible, the effect of this condition is identified by the
validity bits in the machine-check interruption code. The
instruction has beennullified or unaffected only if the
associated validity bits are set to ones.
Interruption Action (Continued)
other than an odd instruction address, and, concur
rently, the LOAD PSW orSUPERVISOR CALL
instruction causes a program event, the ILC is0, as called for in the specification exception.
ILC on Instruction Fetch Exceptions
When a program interruption occurs because of an
exception that prohibits access to the instruction, the
instruction-length code cannot be set on the basis of
the first two bits of the instruction. As far as the
significance of the ILC for this case is concerned,
the following two situations are distinguished:
1. When an odd instruction address causes a spec
ification exception to be recognized or when a
protection, addressing, or translation
specification exception is encountered on
fetching an instruction, the instruction-length
code is 1, 2, or 3, indicating the number of
halfwords by which the instruction address has
been incremented. When the instruction ad
dress in the old PSW is reduced by the number
of halfword locations indicated by the
instruction-length code, the address originally
appearing in the PSW is obtained. It is unpre
dictable whether the code is 1, 2, or 3.
2. When a segment-translation or page-translation
exception is recognized on the access to an
instruction, the ILC is 1, 2, or 3, with the indi
cation being unpredictable. In this case the op
eration is nullified, and the instruction address
is not incremented.
The ILC is not necessarily related to the first two
bits of the instruction when the first halfword of an
instruction can be fetched but an access exception is
recognized on fetching the second or third halfword.
+ Plus thefollowing bits in the control register.
*In BC mode, program-event recording is disabled. c Channel address bits.
d Device address bits.
e A possible nonzero code indicating another program
interruption condition.
m Bits of model-dependent code.
n Possible bit-significant indication of other concurrent
interruption conditions.
r Bits of theI field of SUPERVISOR CALL.
x Unpredictable in BC mode; not stored in EC mode.
When any exceptions are encountered on fetching
the subject instruction of EXECUTE, the ILC is 2.
Programming Notes
A nonzero instruction-length code for a program
interruption indicates the number of halfword loca
tions by which the instruction address in the old
PSW must be reduced to obtain the address of the
last instruction executed, unless one of the following
situations exists:
1. The interruption is caused by a segment
translation or page-translation exception.
2. An interruption for a program event occurs
before the completion of the execution of an
interruptible instruction.
3. The interruption is caused by a program event
due to a branch instruction, LOAD PSW, orSUPERVISOR CALL.
4. The interruption is caused by an access excep
tion encountered in fetching an instruction,
and the instruction address has been intro
duced into the PSW by a means other than
sequential operation (by a branch instruction,
LOAD PSW, or an interruption).
S. The interruption is caused by a specification
exception becauseof an odd instruction ad
dress.
6. The interruption is caused by a specification or
access exception encountered in fetching an
instruction, and changes have been made or
may have been made to the parameters that
control the relation between the logical and
real instruction address (turning the translation
mode on or off without introducing an entire
new PSW, changing the translation-control
Interruptions 73
A machine-check interruption code of 64 bits is stored at
locations 232-239.
2 When the interruption code indicates a program event, an
of zero may be stored only when the code formed by bits
12-15 of the interruption code has a nonzero value.
3 The unit of operation is completed, unless a program exception
concurrently indicated has caused the unit of operation to be
4
5 For channels
effect in BC mode.
6 Bits 16-31 in the
interruption code is provided in EC mode.
7 For any machine-check interruption condition, either exigent
or repressible, the effect of this condition is identified by the
validity bits in the machine-check interruption code. The
instruction has been
associated validity bits are set to ones.
Interruption Action (Continued)
other than an odd instruction address, and, concur
rently, the LOAD PSW or
instruction causes a program event, the ILC is
ILC on Instruction Fetch Exceptions
When a program interruption occurs because of an
exception that prohibits access to the instruction, the
instruction-length code cannot be set on the basis of
the first two bits of the instruction. As far as the
significance of the ILC for this case is concerned,
the following two situations are distinguished:
1. When an odd instruction address causes a spec
ification exception to be recognized or when a
protection, addressing, or translation
specification exception is encountered on
fetching an instruction, the instruction-length
code is 1, 2, or 3, indicating the number of
halfwords by which the instruction address has
been incremented. When the instruction ad
dress in the old PSW is reduced by the number
of halfword locations indicated by the
instruction-length code, the address originally
appearing in the PSW is obtained. It is unpre
dictable whether the code is 1, 2, or 3.
2. When a segment-translation or page-translation
exception is recognized on the access to an
instruction, the ILC is 1, 2, or 3, with the indi
cation being unpredictable. In this case the op
eration is nullified, and the instruction address
is not incremented.
The ILC is not necessarily related to the first two
bits of the instruction when the first halfword of an
instruction can be fetched but an access exception is
recognized on fetching the second or third halfword.
+ Plus the
*
d Device address bits.
e A possible nonzero code indicating another program
interruption condition.
m Bits of model-dependent code.
n Possible bit-significant indication of other concurrent
interruption conditions.
r Bits of the
x Unpredictable in BC mode; not stored in EC mode.
When any exceptions are encountered on fetching
the subject instruction of EXECUTE, the ILC is 2.
Programming Notes
A nonzero instruction-length code for a program
interruption indicates the number of halfword loca
tions by which the instruction address in the old
PSW must be reduced to obtain the address of the
last instruction executed, unless one of the following
situations exists:
1. The interruption is caused by a segment
translation or page-translation exception.
2. An interruption for a program event occurs
before the completion of the execution of an
interruptible instruction.
3. The interruption is caused by a program event
due to a branch instruction, LOAD PSW, or
4. The interruption is caused by an access excep
tion encountered in fetching an instruction,
and the instruction address has been intro
duced into the PSW by a means other than
sequential operation (by a branch instruction,
LOAD PSW, or an interruption).
S. The interruption is caused by a specification
exception because
dress.
6. The interruption is caused by a specification or
access exception encountered in fetching an
instruction, and changes have been made or
may have been made to the parameters that
control the relation between the logical and
real instruction address (turning the translation
mode on or off without introducing an entire
new PSW, changing the translation-control
Interruptions 73