By TNL: GN22-0498
Conversely, the request is not cleared by the inter
ruption, and, if the condition persists, more than one
interruption may result from a single occurrence of
the condition.
interruption code of
zeros
control register
An interruption request for the
the
before the request is honored, the request does not
remain pending, and no interruption occurs. Con
versely, the request is not cleared by the interrup
tion, and, if the condition persists, more than one
interruption may occur from a single occurrence of
the condition.
The condition is indicated by an external
interruption code of
zeros are stored at locations 132-133.
The submask bit is located in bit position 21 of
control register
Input/Output Interruption
The input/output
means by which the
An
stored at location 56, a channel status word to be
stored at location 64, and a new
from location
errors, additional information may be stored in the
form of a limited channel logout at location 176 and
in the form of an
location designated by the contents of locations 173-
175.
When the old
interruption code in
fies the channel and device causing the interruption:
the channel address appears in the high-order eight
bit positions and the device address in the low-order
eight. The·instruction-Iength code is unpredictable.
When the old
vice address is placed at location 187, the channel
tion
senting the request. Whether the
interruption by a channel is controlled by mask bits
88 System/370 Principles of Operation
in the
2, and the method of control depends on whether
the current
Channel mask bits are located in control register
2 starting at bit position
contiguous bit positions as the number of channels
provided. The assignment is such that a bit is as
signed to the channel whose address is equal to the
position of the bit in control register 2. Channel
mask bits for installed channels are initialized to one.
The state of channel mask bits for unavailable chan
nels is unpredictable.
When the current
interruptions from channels 6 and up are controlled
by the
the corresponding channel mask bit: the channel can
cause an interruption only when the
and the corresponding channel mask is one. Interrup
tions from channels
masks
only when the mask corresponding to the channel is
one. In the BC mode, bits
do not participate in controlling
they are, however, preserved in the control register.
When the current
each channel is controlled by the
the corresponding channel mask bit in control regis
ter 2: the channel can cause an interruption only
when the
channel mask bit is one.
When the
I/O-interruption condition, the interruption occurs
at the completion of the instruction execution or
interruption that causes the enabling.
A request for an
any time, and more than one request may occur at
the same time. The requests are preserved and re
main pending in channels or devices until accepted
by the
so that only one interruption request is processed at
a time. For more
1
Restart
The restart interruption
operator or another
a program. The
interruption.
A restart interruption causes the old
stored at main-storage location 8 and a new
be fetched from location
instruction-length code in the