der code is interpreted as described under
the heading "Status Bits. " When any of the conditions described in 3 and 4
exists, the addressed CPU is referred to as "busy." Busy is not indicated if the addressed CPU is in the
check-stop state or when the operator-intervening
condition exists. A GPU-busy condition is normally
of short duration; however, the conditions described
in item 3 may last indefinitely because of an unend­
ing series of interruptions or because of an invalid
address in the prefix register. In this situation, how­
ever, the CPU does not appear busy to any of the
reset orders or to IMPL.
Status Bits
Eight status conditions are defined whereby the issu­
ing and addressed CPUs can indicate their response
to the designated order. The status conditions and
their bit positions in the general register designated
by the Rl field of the SIGNAL PROCESSOR in­
struction are as follows:
Bit Position Status Condition 0 Equ i pment check 1·23 Unassigned; zeros stored
24 External-call pending
25 Stopped
26 Operator intervening
27 Check stop
28 Not ready
29 Unassigned; zero stored 30 Invalid order
31 Receiver check
The status condition assigned to bit position 0 is
generated by the CPU executing the SIGNAL PROCESSOR instruction. The status conditions
assigned to bit positions 24-31 are generated by the
addressed CPU.
When the access path to the addressed CPU is
not busy and the addressed CPU is operational and
does not indicate busy to the currently specified
order, the addressed CPU presents its status to the
issuing CPU. These status bits are of two types: • Status bits 24-28 indicate the presence of the
corresponding conditions in the addressed CPU at the time the order code is received.
Except in response to the sense order, each
condition is indicated only when the condition
precludes the successful execution of the desig­
nated order. In the case of sense, all existing
status conditions are indicated; the operator­
intervening and not-ready conditions each are
indicated if these conditions preclude the exe­
cution of any installed order. • Status bits 30 and 31 indicate that the corre­
sponding conditions were detected by the ad­
dressed CPU during reception of the order.
If the presented status is all zeros, the addressed CPU has accepted the order, and condition code 0 is
set at the issuing CPU; if the presented status is not
all zeros, the addressed CPU has rejected the order,
the presented status is stored at the issuing CPU in
the general register designated by the Rl field of the SIGNAL PROCESSOR instruction, zeros are stored
in bit positions 0-23 of the register, and condition
code 1 is set.
When the equipment-check condition exists, bit 0 of the general register designated by the Rl field of
the SIGNAL PROCESSOR instruction is set to one,
bits 1-23 are set to zeros, and the contents of bit
positions 24-31 are unpredictable. In this case, con­
dition code 1 is set independently of whether the
access path to the addressed CPU is busy and inde­
pendently of whether the addressed CPU is not op­
erational, is busy, or has presented zero status.
The status conditions are defined as follows:
Equipment Check: This condition exists when the CPU executing the instruction detects equipment
malfunctioning that has affected only the execution
of this instruction and the associated order. The or­
der code mayor may not have been transmitted, and
mayor may not have been accepted, and the status
bits provided by the addressed processor may be in
error.
External Call Pending: This condition exists when
an external-call interruption condition is pending in
the addressed CPU because of a previously issued SIGNAL PROCESSOR instruction. The condition
exists from the time an external-call order is accept­
ed until the resultant external interruption has been
completed. The condition may be due to the issuing CPU or another CPU. The condition, when present,
is indicated only in response to sense and to external
call.
Stopped: This condition exists when the addressed CPU is in the stopped state. The condition, when
present, is indicated only in response to sense.
Operator Intervening: This condition exists when
the addressed CPU is executing certain operations
initiated from the console or the remote operator
control panel. The particular manually initiated op­
erations that cause this condition to be present de­
pend on the model and on the order specified. This
condition, when present, can be indicated in re­
sponse to all orders. Operator intervening is indicat-
Multiprocessing 99

ed in response to sense if the condition is present
and precludes the acceptance of any of the installed
orders. The condition may also be indicated in re­
sponse to unassigned or uninstalled orders.
Check Stop: This condition exists when the ad­
dressed CPU is in the check-stop state. The condi­
tion, when present, is indicated only in response to
sense, external call, emergency signal, start, stop,
restart, and stop and store status. The condition may
also be indicated in response to unassigned or unin-
stalled orders. . .
Not Ready: This condition exists when the ad­
dressed CPU uses reloadable control storage to per­
form an order and the required microprogram is not
loaded. The not-ready condition may be indicated in
response to all orders except IMPL.
Invalid Order: This condition exists during the com­
munications associated with the execution of SIG­ NAL PROCESSOR when the addressed CPU de­
codes an unassigned or uninstalled order code.
Receiver Check 1= I nval id Order
Not Ready
l Check Stop Operator Intervening #
Stopped -
External Call Pending
Sense X X X X X
External Celli X 0 X X X
Emergency Signal 0 0 X X X
Start 0 0 X X X
Stop 0 0 X X X
Restart 0 0 X X X Initial Progrram Reset 0 0 X 0 X
Program Reset 0 0 X 0 X
Stop and Store Status 0 0 X X X IMPL* 0 0 X 0 0 Initial CPU Reset* 0 0 X 0 X CPU 0 a X 0 X
Unassigned Order 0 0 X O/X X
Explanation: 0 0 0 0 0 0 0 0 0 0 0 0 Receiver Check: This condition exists when the
addressed CPU detects malfunctioning of equipment
during the communications associated with the exe­
cution of SIGNAL PROCESSOR. When this condi­
tion is indicated, the order has not been initiated
and, since the malfunction may have affected the
generation of the remaining receiver status bits,
these bits are not necessarily valid. A machine-check
condition mayor may not have been generated at
the addressed CPU. The following chart summarizes which status con­
ditions are presented to the issuing CPU in response
to each order code.
If the presented status bits are all zeros, the order
has been accepted, and the issuing processor sets
condition code O. If one or more ones are presented,
the order has been rejected, and the issuing proces­
so'r stores the status in the general register specified
by the Rl field of the SIGP instruction and sets
condition code 1.
Programming Notes
A CPU can obtain the following functions by
addressing SIGNAL PROCESSOR to itself:
1. Sense indicates whether an external-call condi­
tion is pending.
X
X
X
X
X
X
X
X
X
X
X
X
X
o A zero is presented in this bit position regardless of the current state of this condition.
1 A one is presented in this bit position. X A zero or a one is presented in this bit position, reflecting the current state of the corresponding condition. O/X Eithl3r a zero or the current state of the corresponding condition is indicated.
# The current state of the condition may depend on the order code that is being interpreted. f If a ()ne is presented in the receiver-check bit position, the values presented in the other bit positions are not
necessarily valid. If the order code is implemented, use the line entry for the order code; if the order code is not implemented, use
the line entry labeled "Unassigned Order." 100 System/370 Principles of Operation