NAME MNEMONIC TYPE Subtract Logical SL RX C
Subtract Norm-
alized (Long) N SD RX F,C
Subtract Norm-
alized (Short) N SE RX F,C
Subtract Un- normalized
(Long)
Subtract Un­ normalized
( Short)
Test Under Mask
Translate
Translate and
Test SW RX F,C SU RX F,C
TM SI C
TR SS TRT SS C UNPK SS EXCEPTIONS CODE NOTE A,S 5F TRM A,S,U,E,LS 6B TRM A,S,U,E,LS 7B TRM
A,S, E,LS 6F TRM
A,S, E,LS 7F TRM
A 91 TRM P,A DC TRM
A DDTRM P,A F3 TRM Unpack Write Direct
Zero and Add 'VRD SI Y M, A 84 TRM ZAP SS T,C P,A, D, DF F8 TRM
The addressing interruption can occur in normal sequential
operation following branching, LOAD PSW, interruption, or man­
ual operation.
Instruction execution is suppressed.
ADDRESSING INTERRUPTION NOTES SPR Operation suppressed
TRM = Operation terminated Specification (S) 1. A data, instruction, or control-word address does
not specify an integral boundary for the unit of in­
formation.
2. The Rl field of an instruction specifies an odd
register address for a pair of general registers that
contain a 64-bit operand.
3. A floating-point register address other than 0, 2,
4, or 6 is specified.
4. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
5. The first operand field is shorter than or equal to
the second operand field in decimal multiplication or
division.
6. The block address specified in SET STORAGE KEY
or INSERT STORAGE KEY has the four low-order bits not
all zero.
7. A psw with nonzero protection key is loaded
when the protection feature is not installed.
In all of these cases the operation is suppressed.
The instruction-length code is 1, 2, or 3.
NAME MNEMONIC Add A
Add Halfword AH
Add Logical AL
Add Normalized
(Long) N ADR
Add Normalized
(Long) N AD
Add Normalized
( Short) N AER
Add NormaHzed
(Short) N AE 150 TYPE RX C
RX C
RX C
RRF,C
RXF,C
RRF,C
RXF,C EXCEPTIONS A,S,
A,S, A,S CODE NOTE IF 5A 4
IF 4A 2
5E 4 S,U,E,LS 2A 3 A,S,U,E,LS 6A 3,8 S,U,E,LS 3A 3 A,S,U,E,LS 7A 3,4
NAME
Add Unnorm­ alized (Long)
Add Unnorm­ alizcd (Long)
Add Un norm­
alized (Short)
Add Unnorm­ alized (Short)
AND
Compare
Compare
I Ialfword
Compare
Logical
Compare
(Long)
Compare
(Long)
Compare
( Short) Compare
( Short)
Convert to
Binary
Convert to
Decimal
Diagnose
Divide
Divide
Divide Dccimal
Dividc (Long)
Divide (Long)
Divide (Short)
Divide (Short) Exclusive OB Execute
Halve (Long)
Halve (Short)
Insert Storage Key
Load
Load and Test (Long) I,oad and (Short) Load Comple­
ment (Long)
Load Comple-
ment (Short)
Load Halfword
Load (Long) I,oad (Long) r,oad Multiple Load Negative
( Long)
Load Negative
(Short)
Load Positive (Long)
T ,oad Positive
(Short)
Load PSW Load (Short) Load (Short)
Multiply
Multiply MNEMONIC AWR
AW AUR AU N
C
CH
CL
CDR
CD
CER
CE
CVB
CVD
DR
D DP NDDR
NDD
NDER
NDE
X
EX
HDR
HER ISK L
LTDR
LTER
LCDR
LCER
LH
LDR
LD
LM
LNDR
LNER LPDR LPER LPS\V LER
LE
MR
M TYPE EXCEPTIONS CODE NOTE
RRF,C
RX,F,C
RRF,C
RXF,C
RX C
RX C
RX C
RX C
RR,F,C
RX,F,C
RR,F,C
RX,F,C S, E,LS 2E 3
A,S, E,LS 6E 3,8 S, E,LS 3E 3
A,S, E,LS 7E 3,4 A,S 54 4 A,S A,S A,S S A,S S A,S 59 4
49 2
55 4
29 3
69 3,8
39 3
79 3,4
RX A,S,D, IK 4F 8
RX SI RR
RX SS T
RRF
RXF
RRF
RXF
RX C
RX
RRF
RRF P,A,S 4E 8
M, A,S 83 S, IK ID 1
A,S, IK 5D 1,4 P,A,S,D, DK FD 5 S,U,E,FK 2D 3
A,S, U ,E,FK 6D 3,8 S,U,E,FK 3D 3 A,S,U,E,FK 7D 3,4 A,S 57 4
A,S, EX 44 2 S 24 3 S 34 3
RRZ M, A,S 09 7
RX A,S RR F,C S RR F,C S RR F,C S RRF,C
RX
RRF
RXF RS RRF,C
RRF,C
RRF,C S A,S S A,S A,S S S S RR F,C S SI L M, A,S RRF S RX FA,S
RR
RX S A,S 58 4
22 3
32 3
23 3
33 3
48 2
28 3
68 3,8
98 4
21 3
31 3 20 3 30 3
82 6,8
38 3
78 3,4
lC 1
5C 1,4

NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Multiply
Decimal MP SS T P,A,S,D FC 5
Multiply
Halfword MH RX A,S 4C 2
Multiply (Long) N MDR RRF S,U,E 2C 3
Multiply (Long) N MD RXF A,S,U,E 6C 3,8
Multiply (Short) N MER RRF S,U,E 3C 3
Multiply (Short) N ME RXF A,S,U,E 7C 3,4 OR 0 RX C A,S 56 4 Set Storage Key SSK RRZ M, A,S 08 7 Shift Left
Double SLDA RS C S, IF 8F 1 Shift Left
Double
Logical SLDL RS S 8D 1 Shift Right
Double SRDA RS C S 8E 1 Shift Right
Double
Logical SRDL RS S 8C 1 Store ST RX P,A,S 50 4 Store IIalfword STH RX P,A,S 40 2 Store (Long) STD RXF P,A,S 60 3,8 Store Multiple STM RS P,A,S 90 4 Store (Short) STE RXF P,A,S 70 3,4
Subtract S RX C A,S, IF 5B 4
Subtract
Halfword SH RX C A,S, IF 4B 2
Subtract
Logical SL RX C A,S 5F 4
Subtract Norm-
alized (Long) NSDR RRF,C S,U,E,LS 2B 3
Subtract Norm-
alized (Long) NSD RXF,C A,S,U,E,LS 6B 3,8
Subtract Norm-
alized (Short) NSER RRF,C S,U,E,LS 3B 3
Subtract Norm-
alized (Short) NSE RXF,C A,S,U,E,LS 7B 3,4
Subtract Un- normalized
(Long) Subtract Un- SWR RRF,C S, E,LS 2F 3
normalized
(Long) SW RXF,C A,S, E,LS 6F 3,8
Subtract Un- normalized
( Short) SUR RRF,C S, E,LS 3F 3
Subtract Un- normalized
( Short) SU RXF,C A,S, E,LS 7F 3,4
The spccification interruption can occur in normal sequential
operation following branching, LOAD psw, intcrruption, or man-
ual operation (Note 1).
The spccification interruption can occur during an interruption
(Note 6). SPECIFICATION INTEnnUPTION NOTES 1 Even register spccification
2 Two-byte unit of information specification
3 Floating-point register specification
4 Four-bytc unit of information specification
5 Decimal multiplier or divisor size specification
6 Zero protection key specification
7 Block address specification
8 Eight-byte unit of information specification
Data (D)
1. The sign or digit codes of operands in decimal
arithmetic, or editing operations, or CONVERT TO BINARY, are incorrect.
2. Fields in decimal arithmetic overlap incorrectly.
3. The decimal multiplicand has too many high­
order significant digits.
The operation is terminated in all three cases.
The instruction-length code is 2 or 3.
NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Add Decimal AP SST,C P,A, D, DF FA 1
Compare
Decimal CP SS T,C A, D F9 1
Convert to
Binary CVB RX A,S,D IK 4F
Divide Decimal DP SS T P,A,S,D, DK FD 1
Edit ED SS T,C P,A, D DE
Edit and Mark EDMK SS T,C P,A, D DF
Multiply
Decimal MP SS T P,A,S,D FC 1,2
Subtract
Decimal SP SS T,C P,A, D, DF FB 1 Zero and Add ZAP SS T,C P,A, D, DF F8 1
All instructions listed may have incorrect codes.
DATA INTEHRUPTION NOTES 1 Overlapping fields 2 Multiplicand length
Fixed-Point Overflow (IF)
A high-order carry occurs or high-order significant bits
are lost in fixed-point addition, subtraction, shifting,
or sign-control operations.
The operation is completed by ignoring the infor­
mation placed outside the register. The interruption
may be masked by psw bit 36.
The instruction-length code is 1 or 2.
NAME MNEMONIC TYPE EXCEPTIONS CODE Add AR RR C IF 1A
Add A RX C A,S, IF 5A
Add Halfword AH RX C A,S, IF 4A
Load Complement LCR RR C IF 13
Load Positive LPH RR C IF 10 Shift Left Double SLDA RS C S, IF 8F Shift Left Single SLA RS C IF 8B Subtract SR RR C IF IB Subtract S RX C A,S, IF 5B Subtract Halfword SH RX C A,S, IF 4B
Fixed-Point Divide (IK) 1. The quotient exceeds the register size in fixed­
point division, including division by zero.
2. The result of CONVERT TO BINARY exceeds 31 bits.
Division is suppressed. Conversion is completed by
ignoring the information placed outside the register.
The instruction -length code is 1 or 2.
NAME MNEMONIC TYPE EXCEPTIONS CODE Convert to Binary CVB RX A,S,D, IK 4F
Divide DR RR S, IK ID Dividc D RX A,S, IK 5D
Appendix G 151