Programming Note
All combinations of register addresses specified by Rl
and Ra are valid. When the register addresses are
equal, only one word is transmitted. When the address
specified by Ra is less than the address specified by R
1
,
the register addresses wrap around from 15 to O. Add
AR RR
lA
7 8 11 12 15
A
RX
5A
7 8 11 12 15 16 1920 31
The second operand is added to the first operand,
and the sum is placed in the first operand location.
Addition is performed by adding all 32 bits of both
operands. If the carries out of the sign-bit position and
the high-order numeric bit position agree, the sum is
satisfactory; if they disagree, an overflow occurs. The
sign bit is not changed after the overflow. A positive
overflow yields a negative final sum, and a negative
overflow results in a positive sum. The overflow causes
a program interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow Program Interruptions:
Addressing (A only)
Specification (A only)
Fixed-point overflow
Programming Note
In two's-complement notation, a zero result is always
positive.
Add Halfword AH RX
4A
7 8 11 12 15 16 1920 31
The halfword second operand is added to the first
operand and the sum is placed in the first operand
location.
The halfword second operand is expanded to a full-
word before the addition by propagating the sign-bit
value through the 16 high-order bit positions.
Addition is performed by adding all 32 bits of both
operands. If the carries out of the sign-bit position
and the high-order numeric bit position agree, the
sum is satisfactory; if they disagree, an overflow oc­
curs. The sign bit is not changed after the overflow.
A positive overflow yields a negative final sum, and a
negative overflow results in a positive sum. The over­
flow causes a program interruption when the fixed­
point overflow mask bit is one.
Resulting Condition Code:
o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow Program Interruptions:
Addressing
Specification
Fixed-point overflow
Add Logical ALR RR
1 E
78 11 12 15
AL RX
5E
78 1112 1516 1920 31
The second operand is added to the first operand, and
the sum is placed in the first operand location. The oc­
currence of a carry out of the sign position is recorded
in the condition code.
Logical addition is performed by adding all 32 bits
of both operands without further change to the result­
ing sign bit. The instruction differs from ADD in the
meaning of the condition code and in the absence of
the interruption for overflow.
If a carry out of the sign position occurs, the leftmost
bit of the condition code (psw bit 34) is made one. In
the absence of a carry, bit 34 is made zero. When the
sum is zero, the rightmost bit of the condition code
(psw bit 35) is made zero. A nonzero sum is indicated
by a one in bit 35.
Resulting Condition Code:
o Sum is zero (no carry)
1 Sum is not zero (no carry)
2 Sum is zero (carry)
3 Sum is not zero (carry)
Fixed-Point Arithmetic 27
Program Interruptions:
Addressing (AL only)
Specification (AL only)
Subtract SR RR I 1B I R1 R2 0 78 11 12 15 S RX I 5B I R1
X
2
B2 D2 0 7 8 11 12 1516 1920 31
The second operand is subtracted from the first op­
erand, and the difference is placed in the first operand
location.
Subtraction is performed by adding the one's com­
plement .of the second operand and a low-order one to
the first operand. All 32 bits of both operands partici­
pate, as in ADD. If the carries out of the sign-bit posi­
tion and the high-order numeric bit position agree, the
difference is satisfactory; if they disagree, an overflow
occurs. The overflow causes a program interruption
when the fixed-point overflow mask bit is one. ResulUng Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow Program Interruptions:
Addressing (S only)
Specifications (S only)
Fixed-point overflow
Programming Note
When the same register is specified as first and second
operand location, subtracting is equivalent to clearing
the register.
Subtracting a maximum negative number from an­
other maximum negative number gives a zero result
and no overflow.
Subtract :Halfword SH RX 4B
7 8 11 12 15 16 1 9 20 31
The halfword second operand is subtracted from the
first operand, and the difference is placed in the first
operand location.
28
The halfword second operand is expanded to a full­
word before the subtraction by propagating the sign­
bit value through 16 high-order bit positions.
Subtraction is performed by adding the one's com­
plement of the expanded second operand and a low­
order one to the first operand. All 32 bits of both op­
erands participate, as in ADD. If the carries out of the
sign-bit position and the high-order numeric bit posi­
tion agree, the difference is satisfactory; if they dis­
agree, an overflow occurs. The overflow causes a pro­
gram interruption when the fixed-point overflow mask
bit is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow Program Interruptions:
Addressing S pecifica tion
Fixed-point overflow
Subtract Logical SLR RR
1 F
78 1112 15 SL RX
5F
7 8 11 1 2 15 16 1 9 20 31
The second operand is subtracted from the first op­
erand, and the difference is placed in the first operand
location. The occurrence of a carry out of the sign
position is recorded in the condition code.
Logical subtraction is performed by adding the one's
complement of the second operand and a low-order
one to the first operand. All 32 bits of both operands
participate, without further change to the resulting
sign bit. The instruction differs from SUBTRACT in the
meaning of the condition code and in the absence of
the interruption for overflow.
If a carry out of the sign position occurs, the left­
most bit of the condition code (psw bit 34) is made
one. In the absence of a carry, bit 34 is made zero.
When the sum is zero, the rightmost bit of the condi­
tion code (psw bit 35) is made zero. A nonzero sum
is indicated by a one in bit 35.
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