Program Interruptions:
Addressing (AL only)
Specification (AL only)
Subtract SR RR I 1B I R1 R2 0 78 11 12 15 S RX I 5B I R1
X
2
B2 D2 0 7 8 11 12 1516 1920 31
The second operand is subtracted from the first op­
erand, and the difference is placed in the first operand
location.
Subtraction is performed by adding the one's com­
plement .of the second operand and a low-order one to
the first operand. All 32 bits of both operands partici­
pate, as in ADD. If the carries out of the sign-bit posi­
tion and the high-order numeric bit position agree, the
difference is satisfactory; if they disagree, an overflow
occurs. The overflow causes a program interruption
when the fixed-point overflow mask bit is one. ResulUng Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow Program Interruptions:
Addressing (S only)
Specifications (S only)
Fixed-point overflow
Programming Note
When the same register is specified as first and second
operand location, subtracting is equivalent to clearing
the register.
Subtracting a maximum negative number from an­
other maximum negative number gives a zero result
and no overflow.
Subtract :Halfword SH RX 4B
7 8 11 12 15 16 1 9 20 31
The halfword second operand is subtracted from the
first operand, and the difference is placed in the first
operand location.
28
The halfword second operand is expanded to a full­
word before the subtraction by propagating the sign­
bit value through 16 high-order bit positions.
Subtraction is performed by adding the one's com­
plement of the expanded second operand and a low­
order one to the first operand. All 32 bits of both op­
erands participate, as in ADD. If the carries out of the
sign-bit position and the high-order numeric bit posi­
tion agree, the difference is satisfactory; if they dis­
agree, an overflow occurs. The overflow causes a pro­
gram interruption when the fixed-point overflow mask
bit is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow Program Interruptions:
Addressing S pecifica tion
Fixed-point overflow
Subtract Logical SLR RR
1 F
78 1112 15 SL RX
5F
7 8 11 1 2 15 16 1 9 20 31
The second operand is subtracted from the first op­
erand, and the difference is placed in the first operand
location. The occurrence of a carry out of the sign
position is recorded in the condition code.
Logical subtraction is performed by adding the one's
complement of the second operand and a low-order
one to the first operand. All 32 bits of both operands
participate, without further change to the resulting
sign bit. The instruction differs from SUBTRACT in the
meaning of the condition code and in the absence of
the interruption for overflow.
If a carry out of the sign position occurs, the left­
most bit of the condition code (psw bit 34) is made
one. In the absence of a carry, bit 34 is made zero.
When the sum is zero, the rightmost bit of the condi­
tion code (psw bit 35) is made zero. A nonzero sum
is indicated by a one in bit 35.

Resulting Condition Code:
o
1 Difference is not zero (no carry)
2 Difference is zero (carry)
3 Difference is not zero (carry) Program Interruptions:
Addressing (SL only)
Specification (SL only)
Programming Note
A zero difference cannot be obtained without a carry
out of the sign position. Compare CR RR I 19 R, R2 0 7 8 11 12 15
C
RX I 59 R, X
2
B2 0 7 8 11 12 1516 1920 31
The first operand is compared with the second op­
erand, and the result determines the setting of the
condition code.
Comparison is algebraic, treating both comparands
as 32-bit signed integers. Operands in registers or
storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 Program Interruptions:
Addressing (C only)
Specification (C only) Compare Halfword CH RX
49
7 8 11 12 15 16 1920 31
The first operand is compared with the halfword sec- ' ond operand, and the result determines the setting of
the condition code.
The halfword second operand is expanded to a full­
word before the comparison by propagating the sign­
bit value through the 16 high-order bit positions.
Comparison is algebraic, treating both comparands
as 32-bit signed integers. Operands in registers or
storage are not changed.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 Program Interruptions:
Addressing
Specification Multiply MR RR
1C
78 1112 15 M RX
5C
7 8 11 1 2 15 1 6 1 9 20 J
31
The product of the multiplier (the second operand)
and the multiplicand (the first operand) replaces the
multiplicand.
Both multiplier and multiplicand are 32-bit signed
integers. The product is always a 64-bit signed integer
and occupies an even/odd register pair. Because the
multiplicand is replaced by the product, the Rl field
of the instruction must refer to an even-numbered reg­
ister. A specification exception occurs when Rl is odd.
The multiplicand is taken from the odd register of the
pair. The content of the even-numbered register re­
placed by the product is ignored, unless the register
contains the multiplier. An overflow cannot occur.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code: The code remains unchanged. Program Interruptions:
Addressing (M only)
Specification
Programming Note
The significant part of the product usually occupics 62
bits or fewer. Only when two maximum negative
numbers are multiplied are 63 significant product bits
formed. Since two's-complement notation is used, the
sign bit is extended right until the first significant
product digit is encountered.
Fixed-Point Arithmetic 29