Multiply Halfword
MH RX 7 8 11 12 15 16 1920 31
The product of the halfword multiplier (second op­
erand) and multiplicand (first operand) replaces the
multiplicand.
Both multiplicand and product are 32-bit signed
integers and may be located in any general register.
The half word multiplier is expanded to a fullword
before multiplication by propagating the sign-bit value
through the 16 high-order bit positions. The multi­
plicand is replaced by the low-order part of the prod­
uct. The bits to the left of the 32 low-order bits are
not tested for significance; no overflow indication is
given.
The sign of the product is determined by the rules
of algebra from the multiplier and multiplicand sign,
except that a zero result is always positive.
Condition Code: The code remains unchanged. Program Interruptions:
Addressing S pecifica tion
Programming Note
The significant part of the product usually occupies 46
bits or fewer, the exception being 47 bits when both
operands are maximum negative. Since the low-order
32 bits of the product are stored unchanged, ignoring
all bits to the left, the sign bit of the result may differ
from the true sign of the product in the case of over­
flow.
Divide
DR RR
1D
7 8 11 12 15
D
RX
5D
7 8 11 1 2 15 16 1 9 20 31
The dividend (first operand) is divided by the divisor
(second operand) and replaced by the quotient and
remainder.
The dividend is a 64-bit signed integer and occupies
the even/odd pair of registers specified by the Rl field
of the instruction. A specification exception occurs 30 when Rl is odd. A 32-bit signed remainder and a
32-bit signed quotient replace the dividend in the
even-numbered and odd-numbered registers, respec­
tively. The divisor is a 32-bit signed integer.
The sign of the quotient is determined by the rules
of algebra. The remainder has the same sign as the
dividend, except that a zero quotient or a zero re­
mainder is always positive. All operands and results
are treated as signed integers. When the relative
magnitude of dividend and divisor is such that the
quotient cannot be expressed by a 32-bit signed integ­
er, a fixed-point divide exception is recognized (a
program interruption occurs, no division takes place,
and the dividend remains unchanged in the gcneral
registers) .
Condition Code: The code remains unchanged. Program Interruptions:
Addressing (D only) S pecifica tion
Fixed-point divide
Programming Note
Division applies to fullword operands in storage only .. Convert to Binary eva RX
4F
7 8 11 12 15 16 1920 31
The radix of the second operand is changed from deci­
mal to binary, and the result is placed in the first
operand location. The number is treated as a right­
aligned signed integer both before and after conver­
sion.
The second operand has the packed decimal data
format and is checked for valid sign and digit codes.
Improper codes are a data exception and cause a pro­
gram interruption. The decimal operand occupies a
double-word storage field, which must be located on
an integral boundary. The low-order four bits of the
field represent the sign. The remaining 60 bits contain
15 binary-coded-decimal digits in true notation. The
packed decimal data format is described under "Deci­ mal Arithmetic." The result of the conversion is placed in the general
register specified by R l The maximum number that
can be converted and still be contained in a 32-bit
register is 2,147,483,647; the minimum number is
-2,147,483,648. For any decimal number outside this
range, the operation is completed by placing the 32
low-order binary bits in the register; a fixed-point
divide exception exists, and a program interruption
follows. In the case of a negative second operand, the
low-order part is in two's-complement notation.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification
Data
Fixed-point divide Convert to Decimal
eVD RX
4E
7 8 1 1 12 15 16 1 9 20 31
The radix of the first operand is changed from binary
to decimal, and the result is stored in the second op­
erand location. The number is treated as a right­
aligned signed integer both before and after con­
version.
The result is placed in the storage location desig­
nated by the second operand and has the packed
decimal format, as described in "Decimal Arithmetic." The result occupies a double-word in storage and must
be located on an integral boundary. The low-order
four bits of the field represent the sign. A positive sign
is encoded as 1100 or 1010; a negative sign is encoded
as 1101 or 1011. The choice between the two sign
representations is determined by the state of psw bit
12. The remaining 60 bits contain 15 binary-cod ed­
decimal digits in true notation.
The number to be converted is obtained as a 32-bit
signed integer from a general register. Since 15 deci­
mal digits are available for the decimal equivalent of
31 bits, an overflow cannot occur.
Condition Code: The code remains unchanged.
Resulting Condition Code: Protection Addressing
Specification Store 5T RX I 50 Rl
X
2
B2 D2 0 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
location.
The 32 bits in the general register are placed un­
changed at the second operand location.
Condition Code: The code remains unchanged.
Program Interruptions: Protection Addressing
Specification Store Halfword
5TH RX 40 7 8 11 12 15 16 1 9 20 31
The first operand is stored at the halfword second
operand location.
The 16 low-order bits in the general register are
placed unchanged at the second operand location. The
16 high-order bits of the first operand do not partici­
pate and are not tested.
Condition Code: The code remains unchanged.
Program Interruptions: Protection Addressing
Specification Store Multiple 5TM R5 90 78 11 12 1516 1920
The set of general registers starting with the register
specified by Rl and ending with the register specified
by R3 is stored at the locations designated by the
second operand address.
The storage area where the contents of the general
registers are placed starts at the location designated
by the second operand address and continues through
as many words as needed. The general registers are
stored in the ascending order of their addresses, start­
ing with the register specified by Rl and continuing
up to and including the register specified by R
3
, with
register 0 following register 15. The first operands
remain unchanged.
Condition Code: The code remains unchanged. Program Interruptions: Protection Addressing S pecifica tion
Fixed-Point Arithmetic 31
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