divide exception exists, and a program interruption
follows. In the case of a negative second operand, the
low-order part is in two's-complement notation.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification
Data
Fixed-point divideConvert to Decimal
eVD RX
4E
7 8 1 1 12 15 16 1 9 20 31
The radix of the first operand is changed from binary
to decimal, and the result is stored in the second op
erand location. The number is treated as a right
aligned signed integer both before and after con
version.
The result is placed in the storage location desig
nated by the second operand and has the packed
decimal format, as described in"Decimal Arithmetic." The result occupies a double-word in storage and must
be located on an integral boundary. The low-order
four bits of the field represent the sign. A positive sign
is encoded as1100 or 1010; a negative sign is encoded
as1101 or 1011. The choice between the two sign
representations is determined by the state of psw bit
12. The remaining60 bits contain 15 binary-cod ed
decimal digits in true notation.
The number to be converted is obtained as a 32-bit
signed integer from a general register.Since 15 deci
mal digits are available for the decimal equivalent of
31 bits, an overflow cannot occur.
Condition Code: The code remains unchanged.
Resulting Condition Code:Protection Addressing
SpecificationStore 5T RX I 50 Rl
X
2
B2 D20 7 8 11 12 1516 1920 31
The first operand is stored at the second operand
location.
The 32 bits in the general register are placed un
changed at the second operand location.
Condition Code: The code remains unchanged.
Program Interruptions:Protection Addressing
SpecificationStore Halfword
5TH RX40 7 8 11 12 15 16 1 9 20 31
The first operand is stored at the halfword second
operand location.
The 16 low-order bits in the general register are
placed unchanged at the second operand location. The
16 high-order bits of the first operand do not partici
pate and are not tested.
Condition Code: The code remains unchanged.
Program Interruptions:Protection Addressing
SpecificationStore Multiple 5TM R5 90 78 11 12 1516 1920
The set of general registers starting with the register
specified by Rl and ending with the register specified
by R3 is stored at the locations designated by the
second operand address.
The storage area where the contents of the general
registers are placed starts at the location designated
by the second operand address and continues through
as many words as needed. The general registers are
stored in the ascending order of their addresses, start
ing with the register specified by Rl and continuing
up to and including the register specified by R
3
, with
register0 following register 15. The first operands
remain unchanged.
Condition Code: The code remains unchanged.Program Interruptions: Protection Addressing S pecifica tion
Fixed-Point Arithmetic 31
follows. In the case of a negative second operand, the
low-order part is in two's-complement notation.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification
Data
Fixed-point divide
eVD RX
4E
7 8 1 1 12 15 16 1 9 20 31
The radix of the first operand is changed from binary
to decimal, and the result is stored in the second op
erand location. The number is treated as a right
aligned signed integer both before and after con
version.
The result is placed in the storage location desig
nated by the second operand and has the packed
decimal format, as described in
be located on an integral boundary. The low-order
four bits of the field represent the sign. A positive sign
is encoded as
as
representations is determined by the state of psw bit
12. The remaining
decimal digits in true notation.
The number to be converted is obtained as a 32-bit
signed integer from a general register.
mal digits are available for the decimal equivalent of
31 bits, an overflow cannot occur.
Condition Code: The code remains unchanged.
Resulting Condition Code:
Specification
X
2
B2 D2
The first operand is stored at the second operand
location.
The 32 bits in the general register are placed un
changed at the second operand location.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
5TH RX
The first operand is stored at the halfword second
operand location.
The 16 low-order bits in the general register are
placed unchanged at the second operand location. The
16 high-order bits of the first operand do not partici
pate and are not tested.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
The set of general registers starting with the register
specified by Rl and ending with the register specified
by R3 is stored at the locations designated by the
second operand address.
The storage area where the contents of the general
registers are placed starts at the location designated
by the second operand address and continues through
as many words as needed. The general registers are
stored in the ascending order of their addresses, start
ing with the register specified by Rl and continuing
up to and including the register specified by R
3
, with
register
remain unchanged.
Condition Code: The code remains unchanged.
Fixed-Point Arithmetic 31