called the first operand. The second operand location
is defined differently for two formats.
In the BB format, the R2 field specifies the address
of a floating-point register containing the second op­
erand. The same register may be specified for the first
and second operand.
In the BX format, the contents of the general register
specified by X2 and B2 arc added to the content of the
D2 field to form an address designating the location of
the second operand.
A zero in an X2 or B2 field indicates the absence of
the corresponding address component.
The register address specified by the Rl and R2
fields should be 0, 2, 4 or 6. Otherwise, a specification
exeception is recognized, and a program interruption
is caused.
The storage address of the second operand should
designate word boundaries for short operands and
double-word boundaries for long operands. Otherwise, a specification exception is recognized, and a program
interruption is caused.
Results replace the first operand, except for the stor­
ing operations, where the second operand is replaced.
Except for the storing of the final result, the contents
of all floating-point or general registers and storage
locations participating in the addressing or execution
part of an operation remain unchanged.
The floating-point instructions are the only instruc­
tions using the floating-point registers.
Instructi,ons
The floating-point arithmetic instructions and their
mnemonics, formats, and operation codes follow. All
operations can be specified in short and long precision
and are part of the floating-point feature. The follow­
ing table indicates when normalization occurs, when
the condition code is set, and the exceptions that
cause a program interruption.
NAME
Load (Long)
Load (Long)
Load (Short)
Load (Short)
Load and Test
(Long)
Load and Test
(Short)
Load Complement
(Long)
Load Complement
(Short)
42
MNEMONIC
LDR
LD
LER
LE
LTDR
LTER
LCDR
LCER TYPE RR F
RX F
RR F
RX F
RR F,C
RR F,C
RR F,C
RR F,C EXCEPTIONS S A,S S A,S S S S S CODE 28
68
38
78
22
32
23
33
NAME MNEMONIC TYPE Load Positive (Long) LPDR Load Positive (Short) LPER Load Negative (Long) LNDR
Load Negative (Short) LNER
Add Normalized
(Long)
Add Normalized
(Long)
Add Normalized
( Short) Add N ormaHzed
( Short) Add U nnormalized
(Long)
Add U nnormalized
(Long)
Add Unnormalized
( Short) Add Unnormalized
( Short) Subtract Normalized
(Long) Subtract Normalized
(Long) Subtract Normalized
( Short) Subtract Normalized
( Short) Subtract Unnorm­
alized (Long) Subtract Unnorm­
alized (Long) Subtract Unnorm­
alized (Short) Subtract Unnorm-
alized (Short)
Compare (Long)
Compare (Long)
Compare (Short)
Compare (Short)
Halve (Long)
Halve (Short)
Multiply (Long)
Multiply (Long)
Multiply (Short)
Multiply (Short) Divide (Long)
Divide (Long)
Divide (Short) Divide (Short) Store (Long) Store (Short) NOTES NADR
NAD
NAER
NAE
AWR
AW AUR AU NSDR NSD NSER NSE SWR SW SUR SU CDR
CD
CER
CE
HDR
HER
NMDR
NMD
NMER
NME
NDDR
NDD
NDER
NDE STD STE A Addressing exception
C Condition code is set
RR F,C BR F,C
RR F,C
RR F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RR F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F,C
RX F,C
RR F
RR F
RR F
RX F
RR F
RX F
RR F
RX F
RR F
RX F
RX F
RX F
E Exponent-overflow exception
F Floating-point feature
FK Floating-point divide exception LS Significance exception
N Normalized operation P Protection exception S Specification exception U Exponent-underflow exception EXCEPTIONS CODE S 20 S 30 S 21 S 31 S,U,E,LS 2A A,S, U ,E,LS 6A S,U,E,LS 3A A,S,U,E,LS 7A S, E,LS 2E A,S, E,LS 6E S, E,LS 3E A,S, E,LS 7E S,U,E,LS 2B A,S,U,E,LS 6B S,U,E,LS 3B A,S,U,E,LS 7B S, E,LS 2F A,S, E,LS 6F S, E,LS 3F A,S, E,LS 7F S 29 A,S 69 S 39 A,S 79 S 24 S 34 S,U,E 2C A,S,U,E 6C S,U,E 3C A,S,U,E 7C S,U,E,FK 2D A,S,U,E,FK 6D S,U,E,FK 3D A,S,U,E,FK 7D P,A,S 60 P,A,S 70
Load
LER RR (Short Operands) I 38 Rl I R2 0 78 11 12 15
LE RX (Short Operands) I 78 Rl I X
2 I B2 0 7 8 11 12 1516 1920 31 LOR RR (Long Operands) I 28 Rl I R2 I 0 7 8 11 12 15 LO RX (Long Operands)
68 Rl I X
2 I B2
7 8 11 12 1516 1920 31
The second operand is placed in the first operand
location.
The second operand is not changed. In short-preci­
sion the low-order half of the result register remains
unchanged. Exponent overflow, exponent underflow,
or lost significance cannot occur.
Condition Code: The code remains unchanged. Program Interruptions:
Operation (if floating-point feature is not in­
stalled)
Addressing (LE, LD only)
Specification
Load and Test
LTER RR
32 LTOR RR
22 (Short Operands)
Rl I R2
7 8 11 12 15
78
(Long Operands)
Rl I R2
11 12 15
The second operand is placed in the first operand
location, and its sign and magnitude determine the
condition code.
The second operand is not changed. In short-preci­
sion the low-order half of the result register remains
unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions:
Operation (if floating -point feature is not in­
stalled)
Specification
Programming Note
When the same register is specified as first and second
operand location, the operation is equivalent to a test
without data movement.
Load Complement LCER RR (Short Operands)
33
78 1112 15 LCOR RR (Long Operands)
23
78 1112 15
The second operand is placed in the first operand
location with the sign changed to the opposite value.
The sign bit of the second operand is inverted, while
characteristic and fraction are not changed. In short­
precision the low-order half of the result register re­
mains unchanged and is not tested.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions:
Operation (if floating-point feature is not in­
stalled)
Specification
Load Positive
LPER RR (Short Operands) 30 78 1112 15 LPOR RR (Long Operands) 20 Rl I R2 I 78 1112 15
The second operand is placed in the first operand
location with the sign made plus.
Floating-Point Arithmetic 43
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