sitions of the initial address. As a consequence, the list
contains 256 eight-bit function bytes. In cases where
it is known that not all eight-bit argument values will
occur, it may be possible to reduce the size of the list.
In a storage-to-storage operation, the operand fields
may be defined in such a way that they overlap. The
effect of this overlap depends upon the operation.
When the operands remain unchanged, as in COMPARE or TRANSLATE AND TEST, overlapping does not affect
the execution of the operation. In the case of MOVE, EDIT, and TRANSLATE, one operand is replaced by new
data, and the execution of the operation may be af­
fected by the amount of overlap and the manner in
which data are fetched or stored. For purposes of
evaluating the effect of overlapped operands, consider
that data are handled one eight-bit byte at a time. All
overlapping fields are considered valid but, in editing,
overlapping fields give unpredictable results.
Condition Code
The results of most logical operations are used to set
the condition code in the psw. The LOAD ADDRESS, IN­ SERT CHARACTERS, STORE CHARACTER, TRANSLATE, and
the moving and shift operations leave this code un­
changed. The condition code can be used for decision­
making by subsequent branch-on-condition instruc­
tions.
The condition code can be set to reHect five types
of results for logical operations: For COMPARE LOGICAL the states 0, 1, or 2 indicate that the first operand is
equal, low, or high.
For the logical-connectives, the states ° or 1 indi­
cate a zero or nonzero result field.
For TEST UNDER MASK, the states 0, 1, or 3 indicate
that the selected bits are all-zero, mixed zero and one,
or all-one,
For TRANSLATE AND TEST, the states 0, 1, or 2 indi­
cate an all-zero function byte, a nonzero function byte
with the operand incompletely tested, or a last func­
tion byte nonzero.
For editing the states 0, 1, or 2 indicate a zero, less
than zero, or greater than zero content of the last re­
sult field. CONDITION CODE SETTING FOR LOGICAL OPEHA TIONS 0 1 2 3
And zero not zero
Compare Logical equal low high
Edit zero < zero > zero
Edit and Mark zero < zero > zero
Exclusive Or zero not zero Or zero not zero
Test Under Mask zero mixed one
Translate and Test zero incomplete complete
Instruction format
Logical instructions use the following five formats:
RR Format I Op Code R1 R2
o 78 1112 15
RX Format Op Code R1
X
2
B2
7 8 11 12 1516 1920 31
R5 Format Op Code R1 R3 B2
7 8 11 12 1516 1920 31
51 Format Op Code
7 8 15 16 1920 31 5S Format Op Code L
B1 I B2 IJ3J 78 1516 1 9 20 31 32 35 36 47
In the RR, RX, and RS formats, the content of the regis­
ter specified by Rl is called the first operand.
In the SI and ss formats, the content of the general
register specified by Bl is added to the content of the
Dl field to form an address. This address deSignates
the leftmost byte of the first operand field. The num­
ber of bytes to the right of this first byte is specified
by the L field in the ss format. In the SI format the size is one byte.
In the RR format, the R2 field specifies the register
containing the second operand. The same register may
be specified for the first and second operand.
In the RX format, the contents of the general regis­
ters specified by the X2 and B2 fields arc added to the
content of the D2 field to form the address of the sec­
ond operand.
In the RS format, used for shift operations, the con­
tent of the general register specified by the B2 field
is added to the content of the D2 field. This sum is not
used as an address but specifies the number of bits of
the shift. The RH field is ignored in the shift oper­
ations.
Logical Operations 51

In the SI format, the second operand is the eight-bit
immediate data field, 12, of the instruction.
In the S8 format, the content of the general register
specified by B2 is added to the content of the D2 field
to form the address of the second operand. The sec­
ond operand field has the same length as the first op­
erand field.
A zero in any of the X2, B1, or B2 fields indicates
the absence of the corresponding address or shift­
amount component. An instruction can specify the
same general register both for address modification
and for operand location. Address modification is al­
ways completed prior to operation execution.
Results replace the first operand, except in STORE CHARACTER, where the result replaces the second op­
erand. A variable-length result is never stored outside
the field specified by the address and length.
The contents of all general registers and storage lo­
cations participating in the addressing or execution of
an operation generally remain unchanged. Exceptions
are the result locations, general register 1 in EDIT AND
MARK, and general registers 1 and 2 in TRANSLATE AND TEST. Instructions
The logicalinstructions, their mnemonics, formats, and
operation codes follow. The table also indicates the
feature to which the instruction belongs, when the
condition code is set, and the exceptions that cause
a program interruption. NAME MNEMONIC TYPE EXCEPTIONS CODE Move MVI SI P,A 92
Move MVC SS P,A D2
Move Numerics MVN SS P,A Dl
Move Zones MVZ SS P,A D3 Compare Logical CLR RR C 15 Compare Logical CL RX C A,S 55 Compare Logical CLI SI C A 95 Compare Logical CLC SS X,C A D5
AND NR RR C 14
AND N RX C A,S 54
AND NI SI C P,A 94
AND NC SS C P,A D4 OR OR RR C 16 OR 0 RX C A,S 56 OR 01 SI C P,A 96 OR OC SS C P,A D6
Exclusive OR XR RR C 17
Exclusive OR X RX C A,S 57
Exclusive OR XI SI, C P,A 97
Exclusive OR XC SS C P,A D7
Test Under Mask TM SI C A 91
Insert Character IC RX A 43 Store Character STC RX P,A 42
Load Address LA RX 41
Translate TR SS P,A DC
Translate and Test TRT SS C A DD
Edit ED SS, T,C P,A, D DE F:dit and Mark EDMK SS, T,C P,A, D DF ,52 NAME MNEMONIC TYPE EXCEPTIONS CODE Shift Left Single Logical SLL RS 89 Shift Right Single Logical SRL RS 88 Shift Left Double
Logical SLDL RS, X S 8D Shift Right Double
Logical SRDL RS, X S 8C NOTES A Addressing exception
C Condition code is set
D Data exception P Protection exception S Specification exception
T Decimal feature
Programming Note
The fixed-point loading and storing instructions also
may be used for logical operations.
Move
MVI 51
92
7 8 1516 1920 31
MVC 55
D2
7 8 1516
The second operand is placed in the first operand lo­
cation.
The ss format is used for a storage-to-storage move.
The SI format introduces one 8-bit byte from the
instruction stream.
In storage-to-storage movement the fields may over­
lap in any desired way. Movement is left to right
through each field a byte at a time.
The bytes to be moved are not changed or in­
spected.
Condition Code: The code remains unchanged. Program Interruptions:
Protection
Addressing
Programming Note
It is possible to propagate one character through an
entire field by having the first operand field start one
character to the right of the second operand field.