In the SI format, the second operand is the eight-bit
immediate data field, 12, of the instruction.
In the S8 format, the content of the general register
specified by B2 is added to the content of the D2 field
to form the address of the second operand. The sec­
ond operand field has the same length as the first op­
erand field.
A zero in any of the X2, B1, or B2 fields indicates
the absence of the corresponding address or shift­
amount component. An instruction can specify the
same general register both for address modification
and for operand location. Address modification is al­
ways completed prior to operation execution.
Results replace the first operand, except in STORE CHARACTER, where the result replaces the second op­
erand. A variable-length result is never stored outside
the field specified by the address and length.
The contents of all general registers and storage lo­
cations participating in the addressing or execution of
an operation generally remain unchanged. Exceptions
are the result locations, general register 1 in EDIT AND
MARK, and general registers 1 and 2 in TRANSLATE AND TEST. Instructions
The logicalinstructions, their mnemonics, formats, and
operation codes follow. The table also indicates the
feature to which the instruction belongs, when the
condition code is set, and the exceptions that cause
a program interruption. NAME MNEMONIC TYPE EXCEPTIONS CODE Move MVI SI P,A 92
Move MVC SS P,A D2
Move Numerics MVN SS P,A Dl
Move Zones MVZ SS P,A D3 Compare Logical CLR RR C 15 Compare Logical CL RX C A,S 55 Compare Logical CLI SI C A 95 Compare Logical CLC SS X,C A D5
AND NR RR C 14
AND N RX C A,S 54
AND NI SI C P,A 94
AND NC SS C P,A D4 OR OR RR C 16 OR 0 RX C A,S 56 OR 01 SI C P,A 96 OR OC SS C P,A D6
Exclusive OR XR RR C 17
Exclusive OR X RX C A,S 57
Exclusive OR XI SI, C P,A 97
Exclusive OR XC SS C P,A D7
Test Under Mask TM SI C A 91
Insert Character IC RX A 43 Store Character STC RX P,A 42
Load Address LA RX 41
Translate TR SS P,A DC
Translate and Test TRT SS C A DD
Edit ED SS, T,C P,A, D DE F:dit and Mark EDMK SS, T,C P,A, D DF ,52 NAME MNEMONIC TYPE EXCEPTIONS CODE Shift Left Single Logical SLL RS 89 Shift Right Single Logical SRL RS 88 Shift Left Double
Logical SLDL RS, X S 8D Shift Right Double
Logical SRDL RS, X S 8C NOTES A Addressing exception
C Condition code is set
D Data exception P Protection exception S Specification exception
T Decimal feature
Programming Note
The fixed-point loading and storing instructions also
may be used for logical operations.
Move
MVI 51
92
7 8 1516 1920 31
MVC 55
D2
7 8 1516
The second operand is placed in the first operand lo­
cation.
The ss format is used for a storage-to-storage move.
The SI format introduces one 8-bit byte from the
instruction stream.
In storage-to-storage movement the fields may over­
lap in any desired way. Movement is left to right
through each field a byte at a time.
The bytes to be moved are not changed or in­
spected.
Condition Code: The code remains unchanged. Program Interruptions:
Protection
Addressing
Programming Note
It is possible to propagate one character through an
entire field by having the first operand field start one
character to the right of the second operand field.

Move Numerics
MVN SS Dl
L
7 8 1516
The low-order four bits of each byte in the second op­
erand field, the numerics, are placed in the low-order
bit positions of the corresponding bytes in the first
operand fields.
The instruction is storage to storage. Movement is
left to right through each field one byte at a time, and
the fields may overlap in any desired way.
The numerics are not changed or checked for validi­
ty. The high-order four bits of each byte, the zones,
remain unchanged in both operand fields.
Condition Code: The code remains unchanged. Program Interruptions:
Protection
Addressing
Move Zones MVZ SS D3
78
L B1 I B2 11m 1516 19 20 31 32 35 36 47
The high-order four bits of each byte in the second
operand field, the zones, are placed in the high-order
four bit positions of the corresponding bytes in the
first operand field.
The instruction is storage to storage. Movement is
left to right through each field one byte at a time, and
the fields may overlap in any desired way.
The zones are not changed or checked for validity.
The low-order four bits of each byte, the numerics,
remain unchanged in both operand fields.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Protection Compare Logical CLR RR I 15 R1 R2 I 0 78 11 12 15
CL RX I 55 R1
X
2 B2 D2 0 78 11 12 1516 1920 31
CLI SI 95
78 15 16 1920 31
CLC SS D5 L B1 I B2 11m 78 1516 19 20 31 32 35 36 47
The first operand is compared with the second oper­
and, and the result is indicated in the condition code.
The instructions allow comparisons that are register
to register, storage to register, instruction to storage,
and storage to storage.
Comparison is binary, and all codes are valid. The
operation proceeds left to right and terminates as soon
as an inequality is found.
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3
Program Interruptions:
Addressing (CL, CLI, CLC only)
Specification (CL only)
Programming Note
The COMPARE LOGICAL is unique in treating all bits
alike as part of an unsigned binary quantity. In vari­
able-length operation, comparison is left to right and
may extend to field lengths of 256 bytes. The oper­
ation may be used for alphameric comparisons.
Logical Operations 53