four bits are inspected for a sign code immediately
after the leftmost four bits are examined.
Any of the plus-sign codes 1010, 1100, 1110, or 1111
will set the S trigger to zero after the digit is in­
spected, whereas the minus-sign codes 1011 and 1101 will leave the S trigger unchanged. When one of these
sign codes is encountered in the four rightmost bits,
these bits no longer are treated as a digit, and a new
character is fetched from storage for the next digit to
be examined.
A plus sign sets the S trigger to zero even if the trig­
ger was set to one for a nonzero digit in the same
source byte or by a significance-start character for that
digit.
Fill Character: The fill character is obtained from
the pattern as part of the editing operation. The first character of the pattern is used as a fill character and
is left unchanged in the result field, except when it is
the digit-.select or significance-start character. In the
latter cases a digit is examined and, when nonzero,
inserted.
Result Condition: To facilitate the blanking of all­
zero fields, the condition code is used to indicate the
sign and zero status of the last field edited. All Jigits
examined are tested for the code 0000. The presence
or absence of an all-zero source field is recorded in the
condition code at the termination of the editing oper­
ation.
1. The condition code is made 0 for a zero source
field, regardless of the state of the S trigger.
2. For a nonzero source field and an S trigger of
one, the code is made 1 to indicate less than zero.
3. For a nonzero source field and an S trigger of
zero, the code is made 2 to indicate greater than zero.
The condition-code setting pertains to fields as spe­
cified by the field-separator characters, regardless of
the number of signs encountered.
For the multiple-field editing operations the con­
dition-code setting reflects only the field following the
last field-separator character. When the last character
of the pattern is a field-separator character, the con­
dition code is made O. The following table gives the details of the edit op­
eration. The leftmost columns give the pattern char­
acter and its code. The next columns snow the states
of the digit and the S trigger used to determine thc
resulting action. The rightmost column shows the new
setting of the S trigger.
58
CHAR- EXAM- TRIG- RESULT TRIG-
ACTER NAME AND INE GER DIGIT CHAR-GER CODE PURPOSE DIGIT STATUS STATUS ACTER SET 0010 0000 digit select yes s=l digit s=O dnotO digit s=l s=O d=O fill 00100001 significance yes s=l digit
start s=O d nota digit s=l s=O d=O fill s=l 00100010 field no fill s=O separator
other message no s=l leave
insertion s=O fill NOTES d Source digit
S trigger (1: minus sign, digits, or pattern used; 0: plus sign, fill used) digit A source digit replaces the pattern character.
fill The fill character replaces the pattern character.
leave The pattern character remains unchanged.
Resulting Condition Code:
o Result field is zero
1 Result field is less than zero
2 Result field is greater than zero
3 Program Interruptions: Operation (if decimal feature is not installed)
Protection
Addressing
Data
Programming Note
As a rule the source operand is shorter than the pat­
tern since it yields two digits or a digit and a sign for
each source number.
When a single instruction is used to edit several
numbers, the zero-field identification is provided only
for the last field.
Edit and Mark
EDMK 55 DF L
B1 I B2 7 8 15 16 19 20 31 32 35 36 47
The format of the source (the second operand) is
changed from packed to zoned and is edited under
control of the pattern (the first operand). The address
of each first significant result digit is recorded in gen­
eral register 1. The edited result replaces the pattern.

The operation is identical to EDIT, except for the ad­
ditional function of inserting a byte address in general
register 1. The use of general register 1 is implied.
The byte address is inserted in bits 8-31 of this regis­
ter. The byte address is inserted each time the S trig­
ger is in the zero state and a nonzero digit is inserted
in the result field. The address is not inserted when
significance is forced by the significance-start charac­
ter of the pattern. Bits 0-7 are not changed.
Resulting Condition Code:
o Result field is zero
1 Result field is less than zero
2 Result field is greater than zero
3
Program Interruptions: Operation (if decimal feature is not installed)
Protection
Addressing
Data
Programming Notes
The EDIT AND MARK facilitates the programming of
floating currency-symbol insertion. The character ad­
dress inserted in register 1 is one more than the ad­
dress where a floating currency-sign would be inserted.
The BRANCH ON COUNT, with zero in the R2 field, may
be used to reduce the inserted address by one.
The character address is not stored when signifl­
cance is forced. Therefore, the address of the charac­
ter following the significance-start character should be
placed in register 1 prior to EDIT AND MARK.
When a single instruction is used to edit several
numbers, the address of the first significant digit of
each number is inserted in general register 1. Only the last address will be available after the instruction
is completed. Shift Left Single SI.L RS
89
7 8 11 12 1516 1920 31
The first operand is shifted left the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. High-order bits are shifted out
without inspection and are lost. Zeros are supplied to
the vacated low-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None. Shift Right Single SRL RS
88
7 8 11 12 1516 1920 31
The first operand is shifted right the number of bits
specified by the second operand address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
All 32 bits of the general register specified by Rl
participate in the shift. Low-order bits are shifted out
without inspection and are lost. Zeros are supplied to
the vacated high-order register positions.
Condition Code: The code remains unchanged.
Program Interruptions: None. Shift Left Double
SLDL RS
80
7 8 11 12 1516 1920 31
The double-length first operand is shifted left the
number of bits specified by the second operand ad­
dress.
The Rl field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. An odd value for Rl is a specification excep­
tion and causes a program interruption. The second
operand address is not used to address data; its low­
order six bits indicate the number of bit positions to
be shifted. The remainder of the address is ignored.
All 64 bits of the even/odd register pair specified
by Rl participate in the shift. High-order bits are
shifted out of the even-numbered register without in­
spection and are lost. Zeros are supplied to the va­
cated low-order positions of the odd-numbered regis­
ters.
Condition Code: The code remains unchanged.
Program Interruptions:
Specification
Logical Operations 59