Load PSW LP5W 51
82
78 15161920 31
The double word at the location designated by the
operand address replaces the psw.
The operand address must have its three low-order
bits zero to designate a double word; otherwise, a
specification exception results in a program interrup
tion.
The double word which is loaded becomes the psw
for the next sequence of instructions. Bits40-63 of the
double word become the new instruction address. The
new instruction address is not checked for available
storage or for an even byte address during a load psw
operation. These checks occur as part of the execution
of the next instructions.
Bits 8-11 of the double word become the new pro
tection key. The protection key must be zero when
the protection feature is not installed; otherwise, the
key is made zero, and a specification exception causes
a program interruption.
The interruption code in bit positions 16-31 of the
new psw is not retained as the psw is loaded. When
the psw is subsequently stored because of an interrup
tion, these bit positions contain a new code. Similarly,
bits 32 and 33 of the psw are not retained uponload ing. They will contain the instruction-length code for
the last-interpreted instruction when the psw is stored
during a branch-and-link operation or during a pro
gram or supervisor-call interruption.
Condition Code: The code is set according to bits
34 and 35 of the new psw loaded.Program Interruptions:
Privileged operation
Addressing
Specification
Programming Note
TheCPU enters the problem state when LOAD psw loads
a double word with a one in bit position 15 and sim
ilarly enters the wait state if bit position 14 is one.
TheLOAD psw is the only instruction available for
entering the problem state or the wait state.
72Set Program Mask
5PM RR04 78 11 12 15
Bits 2-7 of the general register specified by the Rlfield replace the condition code and the program mask bits
of the current psw.
Bits0, 1, and 8-31 of the register specified by the Rl field are ignored. The contents of the register specified
by the R 1field remain unchanged.
The instruction permits setting of the condition code
and the mask bits in either the problem or supervisor
state.
Condition Code: The code is set according to bits
2 and 3 of the register specified by R1.Program Interruptions: None.
Programming Note
Bits 2-7 of the general register may have been loaded
from the psw byBRANCH AND LINK. Set System Mask 5SM 51 80 78 1516 1920 31
The byte at the location designated by the operand
address replaces the system mask bits of the current
psw.
Condition Code: The code remains unchanged.Program Interruptions:
Privileged operation
Addressing
SupervisorCall SVC RR I OA R] R2 I o 78 11 12 15
The instruction causes a supervisor-call interruption,
with the Rl and R2field of the instruction providing
the intenuption code.
82
78 1516
The double word at the location designated by the
operand address replaces the psw.
The operand address must have its three low-order
bits zero to designate a double word; otherwise, a
specification exception results in a program interrup
tion.
The double word which is loaded becomes the psw
for the next sequence of instructions. Bits
double word become the new instruction address. The
new instruction address is not checked for available
storage or for an even byte address during a load psw
operation. These checks occur as part of the execution
of the next instructions.
Bits 8-11 of the double word become the new pro
tection key. The protection key must be zero when
the protection feature is not installed; otherwise, the
key is made zero, and a specification exception causes
a program interruption.
The interruption code in bit positions 16-31 of the
new psw is not retained as the psw is loaded. When
the psw is subsequently stored because of an interrup
tion, these bit positions contain a new code. Similarly,
bits 32 and 33 of the psw are not retained upon
the last-interpreted instruction when the psw is stored
during a branch-and-link operation or during a pro
gram or supervisor-call interruption.
Condition Code: The code is set according to bits
34 and 35 of the new psw loaded.
Privileged operation
Addressing
Specification
Programming Note
The
a double word with a one in bit position 15 and sim
ilarly enters the wait state if bit position 14 is one.
The
entering the problem state or the wait state.
72
5PM RR
Bits 2-7 of the general register specified by the Rl
of the current psw.
Bits
by the R 1
The instruction permits setting of the condition code
and the mask bits in either the problem or supervisor
state.
Condition Code: The code is set according to bits
2 and 3 of the register specified by R1.
Programming Note
Bits 2-7 of the general register may have been loaded
from the psw by
The byte at the location designated by the operand
address replaces the system mask bits of the current
psw.
Condition Code: The code remains unchanged.
Privileged operation
Addressing
Supervisor
The instruction causes a supervisor-call interruption,
with the Rl and R2
the intenuption code.