Load PSW LP5W 51
82
78 1516 1920 31
The double word at the location designated by the
operand address replaces the psw.
The operand address must have its three low-order
bits zero to designate a double word; otherwise, a
specification exception results in a program interrup­
tion.
The double word which is loaded becomes the psw
for the next sequence of instructions. Bits 40-63 of the
double word become the new instruction address. The
new instruction address is not checked for available
storage or for an even byte address during a load psw
operation. These checks occur as part of the execution
of the next instructions.
Bits 8-11 of the double word become the new pro­
tection key. The protection key must be zero when
the protection feature is not installed; otherwise, the
key is made zero, and a specification exception causes
a program interruption.
The interruption code in bit positions 16-31 of the
new psw is not retained as the psw is loaded. When
the psw is subsequently stored because of an interrup­
tion, these bit positions contain a new code. Similarly,
bits 32 and 33 of the psw are not retained upon load­ ing. They will contain the instruction-length code for
the last-interpreted instruction when the psw is stored
during a branch-and-link operation or during a pro­
gram or supervisor-call interruption.
Condition Code: The code is set according to bits
34 and 35 of the new psw loaded. Program Interruptions:
Privileged operation
Addressing
Specification
Programming Note
The CPU enters the problem state when LOAD psw loads
a double word with a one in bit position 15 and sim­
ilarly enters the wait state if bit position 14 is one.
The LOAD psw is the only instruction available for
entering the problem state or the wait state.
72 Set Program Mask
5PM RR 04 78 11 12 15
Bits 2-7 of the general register specified by the Rl field replace the condition code and the program mask bits
of the current psw.
Bits 0, 1, and 8-31 of the register specified by the Rl field are ignored. The contents of the register specified
by the R 1 field remain unchanged.
The instruction permits setting of the condition code
and the mask bits in either the problem or supervisor
state.
Condition Code: The code is set according to bits
2 and 3 of the register specified by R1. Program Interruptions: None.
Programming Note
Bits 2-7 of the general register may have been loaded
from the psw by BRANCH AND LINK. Set System Mask 5SM 51 80 78 1516 1920 31
The byte at the location designated by the operand
address replaces the system mask bits of the current
psw.
Condition Code: The code remains unchanged. Program Interruptions:
Privileged operation
Addressing
Supervisor Call SVC RR I OA R] R2 I o 78 11 12 15
The instruction causes a supervisor-call interruption,
with the Rl and R2 field of the instruction providing
the intenuption code.
The contents of bit positions 8-15 of the instruction
are placed in bit positions 24-31 of the old psw which
is stored in the course of the interruption. Bit positions
16-23 of the old psw are made zero. The old psw is
stored at location 32, and a new psw is obtained from
location 96. The instruction is valid in both problem
and supervisor state.
Condition Code: The code remains unchanged in
the old psw.
Program Interruptions: None.
Set Storage Key 55K RR 08 7 8 11 12 15
The key of the storage block addressed by the register
designated by R2 is set according to the key in the
register designated by R
1
.
The storage block of 2,048 bytes, located on a mul­
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits 0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex­
ception causes a program interruption.
The four-bit storage key is obtained from bits 24-27
of the register designated by the Rl field. Bits 0-23 and
28-31 of this register are ignored.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if protection feature is not installed)
Privileged operation
Addressing
Specification Insert Storage Key
15K RR 09 7 8 11 12 15
The key of the storage block addressed by the reg­
ister designated by R2 is inserted in the register desig­
nated by R1.
The storage block 2,048 bytes, located on a mul­
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits 0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex­
ception causes a program interruption. The four-bit
storage key is inserted in bits 24-27 of the register
specified by the Rl field. Bits 0-23 of this register re­
main unchanged, and bits 28-31 are set to zero.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if protection feature is not installed)
Privileged operation
Addressing
Specification
Write Direct
WRD 51 84 __ __ . _____ D_l ______ ]
78 1516 1920 31
The byte at the location designated by the operand
address is made available as a set of direct-out static
signals. Eight instruction bits are made available as
signal-out timing signals.
The eight data bits of the byte fetched from storage
are presented on a set of eight direct-out lines as
static signals. These signals remain until the next
WRITE DIRECT is executed. No parity is presented with
the eight data bits.
Instruction bits 8-15, the I2 field, are made available
simultaneously on a set of eight signal-out lines as 0.5-
microsecond to 1.0-microsecond timing signals. On a
ninth line (write out) a 0.5-microsecond to 1.0-micro­
second timing signal is made available coincident with
these timing signals. The leading edge of the timing
signals coincides with the leading edge of the data
signals. The eight signal-out lines are also used in
READ DIRECT. No parity is made available with the
eight instruction bits.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if direct control feature is not installed)
Privileged operation
Addressing
Programming Note
The timing signals and the write-out signal may be
used to alert the equipment to which the data are
sent. When data are sent to another CPU, the external
signal interruption may be used to alert that CPU. Status Switching 73
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