The contents of bit positions 8-15 of the instruction
are placed in bit positions 24-31 of the old psw which
is stored in the course of the interruption. Bit positions
16-23 of the old psw are made zero. The old psw is
stored at location 32, and a new psw is obtained from
location 96. The instruction is valid in both problem
and supervisor state.
Condition Code: The code remains unchanged in
the old psw.
Program Interruptions: None.
Set Storage Key55K RR 08 7 8 11 12 15
The key of the storage block addressed by the register
designated by R2 is set according to the key in the
register designated by R
1
.
The storage block of 2,048 bytes, located on a mul
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex
ception causes a program interruption.
The four-bit storage key is obtained from bits 24-27
of the register designated by the Rl field. Bits 0-23 and
28-31 of this register are ignored.
Condition Code: The code remains unchanged.
Program Interruptions:Operation (if protection feature is not installed)
Privileged operation
Addressing
SpecificationInsert Storage Key
15KRR 09 7 8 11 12 15
The key of the storage block addressed by the reg
ister designated by R2 is inserted in the register desig
nated by R1.
The storage block 2,048 bytes, located on a mul
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex
ception causes a program interruption. The four-bit
storage key is inserted in bits 24-27 of the register
specified by the Rl field. Bits 0-23 of this register re
main unchanged, and bits 28-31 are set to zero.
Condition Code: The code remains unchanged.
Program Interruptions:Operation (if protection feature is not installed)
Privileged operation
Addressing
Specification
Write Direct
WRD51 84 __ __ . _____ D_l ______ ]
78 15161920 31
The byte at the location designated by the operand
address is made available as a set of direct-out static
signals. Eight instruction bits are made available as
signal-out timing signals.
The eight data bits of the byte fetched from storage
are presented on a set of eight direct-out lines as
static signals. These signals remain until the next
WRITEDIRECT is executed. No parity is presented with
the eight data bits.
Instruction bits 8-15, theI2 field, are made available
simultaneously on a set of eight signal-out lines as 0.5-
microsecond to 1.0-microsecond timing signals.On a
ninth line (write out) a 0.5-microsecond to 1.0-micro
second timing signal is made available coincident with
these timing signals. The leading edge of the timing
signals coincides with the leading edge of the data
signals. The eight signal-out lines are also used in
READDIRECT. No parity is made available with the
eight instruction bits.
Condition Code: The code remains unchanged.
Program Interruptions:Operation (if direct control feature is not installed)
Privileged operation
Addressing
Programming Note
The timing signals and the write-out signal may be
used to alert the equipment to which the data are
sent. When data are sent to anotherCPU, the external
signal interruption may be used to alert thatCPU. Status Switching 73
are placed in bit positions 24-31 of the old psw which
is stored in the course of the interruption. Bit positions
16-23 of the old psw are made zero. The old psw is
stored at location 32, and a new psw is obtained from
location 96. The instruction is valid in both problem
and supervisor state.
Condition Code: The code remains unchanged in
the old psw.
Program Interruptions: None.
Set Storage Key
The key of the storage block addressed by the register
designated by R2 is set according to the key in the
register designated by R
1
.
The storage block of 2,048 bytes, located on a mul
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex
ception causes a program interruption.
The four-bit storage key is obtained from bits 24-27
of the register designated by the Rl field. Bits 0-23 and
28-31 of this register are ignored.
Condition Code: The code remains unchanged.
Program Interruptions:
Privileged operation
Addressing
Specification
15K
The key of the storage block addressed by the reg
ister designated by R2 is inserted in the register desig
nated by R1.
The storage block 2,048 bytes, located on a mul
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex
ception causes a program interruption. The four-bit
storage key is inserted in bits 24-27 of the register
specified by the Rl field. Bits 0-23 of this register re
main unchanged, and bits 28-31 are set to zero.
Condition Code: The code remains unchanged.
Program Interruptions:
Privileged operation
Addressing
Specification
Write Direct
WRD
78 1516
The byte at the location designated by the operand
address is made available as a set of direct-out static
signals. Eight instruction bits are made available as
signal-out timing signals.
The eight data bits of the byte fetched from storage
are presented on a set of eight direct-out lines as
static signals. These signals remain until the next
WRITE
the eight data bits.
Instruction bits 8-15, the
simultaneously on a set of eight signal-out lines as 0.5-
microsecond to 1.0-microsecond timing signals.
ninth line (write out) a 0.5-microsecond to 1.0-micro
second timing signal is made available coincident with
these timing signals. The leading edge of the timing
signals coincides with the leading edge of the data
signals. The eight signal-out lines are also used in
READ
eight instruction bits.
Condition Code: The code remains unchanged.
Program Interruptions:
Privileged operation
Addressing
Programming Note
The timing signals and the write-out signal may be
used to alert the equipment to which the data are
sent. When data are sent to another
signal interruption may be used to alert that