The contents of bit positions 8-15 of the instruction
are placed in bit positions 24-31 of the old psw which
is stored in the course of the interruption. Bit positions
16-23 of the old psw are made zero. The old psw is
stored at location 32, and a new psw is obtained from
location 96. The instruction is valid in both problem
and supervisor state.
Condition Code: The code remains unchanged in
the old psw.
Program Interruptions: None.
Set Storage Key 55K RR 08 7 8 11 12 15
The key of the storage block addressed by the register
designated by R2 is set according to the key in the
register designated by R
1
.
The storage block of 2,048 bytes, located on a mul­
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits 0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex­
ception causes a program interruption.
The four-bit storage key is obtained from bits 24-27
of the register designated by the Rl field. Bits 0-23 and
28-31 of this register are ignored.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if protection feature is not installed)
Privileged operation
Addressing
Specification Insert Storage Key
15K RR 09 7 8 11 12 15
The key of the storage block addressed by the reg­
ister designated by R2 is inserted in the register desig­
nated by R1.
The storage block 2,048 bytes, located on a mul­
tiple of the block length, is addressed by bits 8-20 of
the register designated by the R2 field. Bits 0-7 and
21-27 of this register are ignored. Bits 28-31 of the
register must be zero; otherwise, a specification ex­
ception causes a program interruption. The four-bit
storage key is inserted in bits 24-27 of the register
specified by the Rl field. Bits 0-23 of this register re­
main unchanged, and bits 28-31 are set to zero.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if protection feature is not installed)
Privileged operation
Addressing
Specification
Write Direct
WRD 51 84 __ __ . _____ D_l ______ ]
78 1516 1920 31
The byte at the location designated by the operand
address is made available as a set of direct-out static
signals. Eight instruction bits are made available as
signal-out timing signals.
The eight data bits of the byte fetched from storage
are presented on a set of eight direct-out lines as
static signals. These signals remain until the next
WRITE DIRECT is executed. No parity is presented with
the eight data bits.
Instruction bits 8-15, the I2 field, are made available
simultaneously on a set of eight signal-out lines as 0.5-
microsecond to 1.0-microsecond timing signals. On a
ninth line (write out) a 0.5-microsecond to 1.0-micro­
second timing signal is made available coincident with
these timing signals. The leading edge of the timing
signals coincides with the leading edge of the data
signals. The eight signal-out lines are also used in
READ DIRECT. No parity is made available with the
eight instruction bits.
Condition Code: The code remains unchanged.
Program Interruptions: Operation (if direct control feature is not installed)
Privileged operation
Addressing
Programming Note
The timing signals and the write-out signal may be
used to alert the equipment to which the data are
sent. When data are sent to another CPU, the external
signal interruption may be used to alert that CPU. Status Switching 73
Read Direct
RDD 51 85
78 15 16 1920 31
Eight instruction bits are made available as signal-out
timing signals. A direct-in data byte is accepted from
an external device in the absence of a hold signal and
is placed in the location designated by the operand
address.
Instruction bits 8-15, the 12 field, are made available
on a set of eight signal-out lines as O.5-microsecond to
l.O-microsecond timing signals. These signal-out lines
are also used in WRITE DIRECT. On a ninth line (Read Out) a O.5-microsecond to l.O-microsecond timing
signal is made available coincident with these timing
signals. The read-out line is distinct from the write-out
line in WRITE DIRECT. No parity is made available with
the eight instruction bits.
Eight data bits are accepted from a set of eight
direct-in Hnes. when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least O.5-microsecond. No parity is ac­
cepted with data signals, but a parity bit is generated
as the data are placed in storage. When the hold sig­
nal is not removed, the CPU does not complete the in­
struction. Excessive duration of this instruction may
result in incomplete updating of the timer.
Condition Code: The code remains unchanged. Program Interruptions: Operation (if direct control feature is not installed)
Privileged operation
Protection
Addressing Programming Note
The direct-out lines of one CPU may be connected to
the direct-in lines of another CPU, providing cpu-to-cpu
static signaling. Further, the write-out signal of the
sending CPU may serve as the hold signal for the re­
ceiving CPU, temporarily inhibiting a READ DIRECT when
the signals are in transition.
Equipment connected to the hold-in line should be
so constructed that the hold signal is removed when
READ DIRECT is performed. Absence of the hold signal
should correspond to absence of current in such a
fashion that the CPU can proceed when power is re­
moved from the source of the hold signal.
74
Diagnose 51 83
78 1516 1920 31
The CPU performs built-in diagnostic functions.
The purpose of the h field and the operand address
may be defined in greater detail for a particular CPU and its appropriate diagnostic procedures. Similarly,
the number of low-order address bits which must be
zero is further specified for a particular CPU. When the
address does not have the required number of low­
order zeros, a specification exception causes a program
interruption.
The purpose of the diagnostic functions is verifica­
tion of proper functioning of the CPU equipment and
locating faulty components.
The DIAGNOSE is completed either by taking the next
sequential instruction or by obtaining a new psw from
location 112. The diagnostic procedure may affect the
problem, supervisor, and interruptable status of the CPU, the condition code, and the contents of storage,
registers, and timer, as well as the progress of 1/0 operations. Some diagnostic functions turn on the test light on
the operator control section of the system control
panel. Since the instruction is not intended for problem­
program or supervisor-program use, DIAGNOSE has no
mnemonic.
Condition Code: The code is unpredictable. Program Interruptions:
Privileged operation
Specification
Addressing
Status-Switching Exceptions
Exceptional instructions or data cause a program in­
terruption. When the interruption occurs, the current
psw is stored as an old PSW, and a new psw is obtained.
Thc interruption code inserted in the old psw identi­
fies the cause of the interruption. The following ex­
ception conditions cause a program interruption in
status-switching operations.
Operation: The direct control feature is not installed,
and the instruction is READ DIRECT or WRITE DIRECT; or,
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