Read Direct
RDD51 85
78 15 161920 31
Eight instruction bits are made available as signal-out
timing signals. A direct-in data byte is accepted from
an external device in the absence of a hold signal and
is placed in the location designated by the operand
address.
Instruction bits 8-15, the12 field, are made available
on a set of eight signal-out lines as O.5-microsecond to
l.O-microsecond timing signals. These signal-out lines
are also used in WRITEDIRECT. On a ninth line (Read Out) a O.5-microsecond to l.O-microsecond timing
signal is made available coincident with these timing
signals. The read-out line is distinct from the write-out
line in WRITEDIRECT. No parity is made available with
the eight instruction bits.
Eight data bits are accepted from a set of eight
direct-inHnes. when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least O.5-microsecond. No parity is ac
cepted with data signals, but a parity bit is generated
as the data are placed in storage. When the hold sig
nal is not removed, theCPU does not complete the in
struction. Excessive duration of this instruction may
result in incomplete updating of the timer.
Condition Code: The code remains unchanged.Program Interruptions: Operation (if direct control feature is not installed)
Privileged operation
Protection
AddressingProgramming Note
The direct-out lines of oneCPU may be connected to
the direct-in lines of anotherCPU, providing cpu-to-cpu
static signaling. Further, the write-out signal of the
sendingCPU may serve as the hold signal for the re
ceivingCPU, temporarily inhibiting a READ DIRECT when
the signals are in transition.
Equipment connected to the hold-in line should be
so constructed that the hold signal is removed when
READDIRECT is performed. Absence of the hold signal
should correspond to absence of current in such a
fashion that theCPU can proceed when power is re
moved from the source of the hold signal.
74
Diagnose51 83
78 15161920 31
TheCPU performs built-in diagnostic functions.
The purpose of theh field and the operand address
may be defined in greater detail for a particularCPU and its appropriate diagnostic procedures. Similarly,
the number of low-order address bits which must be
zero is further specified for a particularCPU. When the
address does not have the required number of low
order zeros, a specification exception causes a program
interruption.
The purpose of the diagnostic functions is verifica
tion of proper functioning of theCPU equipment and
locating faulty components.
TheDIAGNOSE is completed either by taking the next
sequential instruction or by obtaining a new psw from
location 112. The diagnostic procedure may affect the
problem, supervisor, and interruptable status of theCPU, the condition code, and the contents of storage,
registers, and timer, as well as the progress of1/0 operations. Some diagnostic functions turn on the test light on
the operator control section of the system control
panel.Since the instruction is not intended for problem
program or supervisor-program use,DIAGNOSE has no
mnemonic.
Condition Code: The code is unpredictable.Program Interruptions:
Privileged operation
Specification
Addressing
Status-Switching Exceptions
Exceptional instructions or data cause a program in
terruption. When the interruption occurs, the current
psw is stored as an oldPSW, and a new psw is obtained.
Thc interruption code inserted in the old psw identi
fies the cause of the interruption. The following ex
ception conditions cause a program interruption in
status-switching operations.
Operation: The direct control feature is not installed,
and the instruction is READDIRECT or WRITE DIRECT; or,
RDD
78 15 16
Eight instruction bits are made available as signal-out
timing signals. A direct-in data byte is accepted from
an external device in the absence of a hold signal and
is placed in the location designated by the operand
address.
Instruction bits 8-15, the
on a set of eight signal-out lines as O.5-microsecond to
l.O-microsecond timing signals. These signal-out lines
are also used in WRITE
signal is made available coincident with these timing
signals. The read-out line is distinct from the write-out
line in WRITE
the eight instruction bits.
Eight data bits are accepted from a set of eight
direct-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least O.5-microsecond. No parity is ac
cepted with data signals, but a parity bit is generated
as the data are placed in storage. When the hold sig
nal is not removed, the
struction. Excessive duration of this instruction may
result in incomplete updating of the timer.
Condition Code: The code remains unchanged.
Privileged operation
Protection
Addressing
The direct-out lines of one
the direct-in lines of another
static signaling. Further, the write-out signal of the
sending
ceiving
the signals are in transition.
Equipment connected to the hold-in line should be
so constructed that the hold signal is removed when
READ
should correspond to absence of current in such a
fashion that the
moved from the source of the hold signal.
74
Diagnose
78 1516
The
The purpose of the
may be defined in greater detail for a particular
the number of low-order address bits which must be
zero is further specified for a particular
address does not have the required number of low
order zeros, a specification exception causes a program
interruption.
The purpose of the diagnostic functions is verifica
tion of proper functioning of the
locating faulty components.
The
sequential instruction or by obtaining a new psw from
location 112. The diagnostic procedure may affect the
problem, supervisor, and interruptable status of the
registers, and timer, as well as the progress of
the operator control section of the system control
panel.
program or supervisor-program use,
mnemonic.
Condition Code: The code is unpredictable.
Privileged operation
Specification
Addressing
Status-Switching Exceptions
Exceptional instructions or data cause a program in
terruption. When the interruption occurs, the current
psw is stored as an old
Thc interruption code inserted in the old psw identi
fies the cause of the interruption. The following ex
ception conditions cause a program interruption in
status-switching operations.
Operation: The direct control feature is not installed,
and the instruction is READ