MACHINE INSTRUCTIONS ® OP FOR· NAME MNEMONIC COOE MAT OPERANOS Add (c) AR lA RR Rl,R2 Add (c) A 5A RX Rl,02(X2,B2) Add Decimal (c) AP FA SS 01 (L l,Bl ),02(L2,B2) Add Halfword (c) AH 4A RX Rl,02(X2,B2) Add Logical (c) ALR lE RR Rl,R2 Add Logical (c) AL 5E RX R l,02(X2,B2) AND (c) NR 14 RR Rl,R2 AND (c) N
54 RX Rl,02(X2,B2) AND (c) NI 94 SI 01(Bl),12 AND (c) NC 04 SS OHL,Bl),02(B2) Branch and Link BALR 05 RR Rl,R2 Branch and Li n k BAL 45 RX Rl.02(X2.B2) Branch on Condition BCR 07 RR Ml.R2 Branch on Condition BC 47 RX Ml,02(X2,B2) Branch on Count BCTR 06 RR Rl,R2 Branch on Count BCT 46 RX Rl,02(X2,B2) Branch on Index High BXH 86 RS R l,R3.02(B2) Branch on Index Low or Equal BXLE 87 RS R l,R3.02(B2) Clear I/O (c,p) CLRIO 9001 S 02(B2) Compare (c) CR 19 RR Rl,R2 Compare (c) C
59 RX Rl,02(X2.B2) Compare and Swap (c) CS BA RS Rl,R3,02(B2) Compare Decimal (c) CP F9 SS 01 (L 1 ,Bl ),02(L2,B2) Compare Double and Swap (c) COS BB RS Rl,R3,02(B2) Compare Halfword (c) CH 49 RX R l,02(X2,B2) Compare Logical (c) CLR 15 RR Rl,R2 Compare Logical (c) CL 55 RX Rl,02(X2,B2) Compare Logical (c) CLC 05 SS 01lL,Bll,02{B2) Compare Logical (c) CLI 95 SI 01(Bl),12 Compare Logical Characters CLM BO RS Rl,M3,02(B2) under Mask (c)
Compare Logical Long (c) CLCL OF RR Rl,R2 Convert to Binary CVB 4F RX Rl,02(X2,B2) Convert to Decimal CVO 4E RX Rl,02(X2,B2) (p) 83 Model-dependent
Divide DR 10 RR Rl,R2 Divide 0 50 RX Rl,02(X2,B2) Divide Decimal OP FO SS 01 (L l,Bl ),02(L2,B2) Edit (c) ED DE SS 01 (L,Bl ),02(B2) Edit and Mark (c) EOMK OF SS 01 (L,Bl ),02(B2) Exclusive OR (c) XR 17 RR Rl,R2 Exclusive OR (c) X 57 RX R l,02(X2,B2) Exclusive OR (e) XI 97 SI 01(Bl),12 Exclusive OR (c) XC 07 SS 01 (L,BlI,02(B2) Execute EX 44 RX Rl,02(X2,B2) Halt I/O (c,p) HIO 9EOO S 02(B2) Halt Device (c,p) HOV 9EOl S 02(B2) I nsert Character IC 43 RX Rl,02(X2,B2) Insert Characters under Mask (c) ICM BF RS Rl,M3,02(B2) Insert PSW Key (pI IPK B20B S Insert Storage Key (p) ISK 09 RR Rl,R2 Load LR 18 RR Rl,R2 Load L 58 RX Rl,02(X2,B2) Load Address LA 41 RX R l,02(X2,B2) Load and Test (c) LTR 12 RR Rl,R2 Load Complement (c) LCR 13 RR Rl,R2 Load Control (p) LCTL B7 RS Rl,R3,02(B2) Load Halfword LH 48 RX Rl,02(X2,B2) Load Multiple LM 98 RS Rl,R3,02(B2) Load Negative (c) LNR 11 RR Rl,R2 Load Positive (c) LPR 10 RR Rl,R2 Load PSW (n,p) LPSW 82 S 02(B2) Load Real Address (c,p) LRA Bl RX R l,02(X2,B2) Monitor Call MC AF SI 01(Bl),12 Move MVI 92 SI 01(B1),12 Move MVC 02 SS 01 (L,Bl ),02(B2) Move Long (c) MVCL OE RR Rl,R2 Move Numerics MVN 01 SS 01(L,Bl ),02(B2) Move with Offset MVO Fl SS 01 (L l,Bl ),02(L2,B2) Move Zones MVZ 03 SS 01 (L,Bl ),02(B2) Multiply MR lC RR Rl,R2 Multiply M 5C RX Rl,02(X2,B2) Multiply Decimal MP FC SS 01 (L l,Bl ),02(L2,B2) Multiply Halfword MH 4C RX Rl,02(X2,B2) OR (c) OR 16 RR Rl,R2

MACHINE INSTRUCTIONS (Contd) OP FOR· OR (c) OR (c) OR (c)
Pack
NAME MNEMONIC o COOE MAT
56 RX OPERANOS R1,02(X2,82) 01(81),12 Purge TLB (p)
Read Direct (p)
Reset Reference Bit (c,p)
Set Clock (c,p)
Set Clock Comparator (p)
Set CPU Timer (p)
Set Prefix (p) Set Program Mask (n)
Set PSW Key from Address (p) Set Storage Key (p) Set System Mask (p)
Shift and Round Decimal (c) Shift Left Double (c) Shift Left Double Logical Shift Left Single Ic) Shift Left Single Logical Shift Right Double (c) Shift Right Double Logical Shift Right Single (c) Shift Right Single Logical
Signal Processor (c,p) Start I/O (c,p)
Start I/O Fast Release (c,p) Store Store ChannellD (c,p) Store Character
Store Characters under Mask
Store Clock (c)
Store Clock Comparator (p)
Store Control (p)
Store CPU Address (p)
Store CPU ID (p)
Store CPU Timer (p) Store Halfword Store Multiple Store Prefix (p)
Store Then AND System
Mask (p)
Store Then OR System Mask (p) Subtract (c) Subtract (c) Subtract Decimal (c) Subtract Halfword (c) Subtract Logical (c) Subtract Logical (c) Supervisor Call Test and Set (c)
Test Channel (c,p)
Test I/O (c,p)
Test under Mask (c)
Translate
Translate and Test (c)
Unpack
Write Direct (p) Zero and Add Decimal (c) Floating-Point Instructions NAME
Add Normalized, Extended (c,x)
Add Normalized, Long (c)
Add Normalized, Long (c)
Add Normalized, Short (c)
Add Normalized, Short (c)
Add Unnormalized, Long (c)
Add Unnormalized, Long (c)
Add Unnormal'ized, Short (c)
Add Unnormalized, Short Ic) c. Condition code is set.
n. New condition code is loaded. 01 OC PACK
PTL8 ROD RR8 SCK SCKC SPT SPX SPM SPKA SSK SSM SRP SLOA SLOL SLA SLL SROA SROL SRA SRL SIGP SIO SIOF ST STIOC STC STCM STCK STCKC STCTL STAP STIOP STPT STH STM STPX STNSM STOSM SR 5 5P SH 5LR SL SVC TS TCH TIO TM
TR
TRT
UNPK WRO ZAP 96 SI 06 5S F2 SS 82005 85 51 8213 S 8204 S 8206 S 8208 5 8210 S 04 RR 820A S 08 RR 80 5 FO 55 8F R5 80 R5
88 RS 89 R5
8E RS 8C R5
8A R5
88 RS AE R5 9COO 5 9C01 S 50 RX 8203 S 42 RX
8E RS 8205 5 8207 S 86 RS 8212 S 8202 S 8209 S 40 RX 90 R5
8211 5
AC 51 AD 51 18 RR
58 RX
F8 S5 48 RX
1F RR SF RX OA RR
93 5 9FOO S 9000 S 91 SI DC SS DO SS F3 SS 84 SI F8 SS 01 (L,81l,02(82) 01 (L 1,81 ),02(L2,82) 01(81),/2 02(82) 02(82) 02(82) 02(82) 02(82) Rl 02(82) R1,R2 02(82) 01 (L 1,81 ),02(82),13 R1,02(82) R1,02(82)
R1,02(82)
R1,02(82)
R1,02(82)
R1,02(82)
R1,02(82)
R1,02(82)
R1,R3,02(82) 02(82) 02(82) R
1,02(X2,82) 02(82) R1,02(X2,82)
R1,M3,02(82) 02(82) 02(82) R1,R3,02(82) 02(82) 02(82) 02(82) R
1,02(X2,82)
R1,R3,02(82) 02(82) 01(81),12 01(81),/2 Rl,R2 Rl,02(X2,82) 01 (L 1,81 ),02(L2,82)
R1,02(X2,82)
R1,R2
R l,02(X2,82) I 02(82) 02(82) 02(82) 01(81),12 01(L,81),02(82) 01 (L,81 ),02(82) 01 (L 1,81 ),02(L2,82) 01(81),12 01 (L 1,81 ),02(L2,82) OP FOR· MNEMONIC AXR AOR AD
AER
AE
AWR
AW
AUR
AU COOE MAT
36 RR
2A RR
6A RX
3A RR
7A RX
2E RR
6E RX
3E RR
7E RX OPERANDS R1,R2
R1,R2 Rl,02(X2,82) R1,R2
R l,02(X2,82) R1,R2 Rl,02(X2,82) R1,R2
R1,02(X2,82)
p. Privileged instruction.
x. Extended precision floating-point.

FloatinltPoint Instructions (Contd) OP FOR· 0 NAME MNEMONIC CODE MAT OPERANDS Compare, Long (c) CDR 29 RR R1,R2 Compare, Long (c) CD 69 RX R1,D2(X2,B2) Compare, Short (c) CER 39 RR R1,R2 Compare, Short (c) CE 79 RX R 1,D2(X2,B2) Divide, Long DDR 20 RR R1,R2 Divide, Long DO 60 RX R1,D2(X2,B2) Divide, Short DER 3D RR R1,R2 Divide, Short DE 70 RX R1,D2(X2,B2) Halve, Long HDR 24 RR R1,R2 Halve, Short HER 34 RR R1,R2 Load and Test, Long (c) LTDR 22 RR R1,R2 Load and Test, Short (c) LTER 32 RR R1,R2 Load Complement, Long (c) LCDR 23 RR R1,R2 Load Complement, Short (c) LCER 33 RR R1,R2 Load, Long LOR 28 RR R1,R2 Load, Long LD 68 RX R1,D2(X2,B2) Load Negative, Long (c) LNDR 21 RR R1,R2 Load Negative, Short (c) LNER 31 RR R1,R2 Load Positive, Long (c) LPDR 20 RR R1,R2 Load Positive, Short (c) LPER 30 RR R1,R2 Load Rounded, Extended to Long (x) LRDR 25 RR R1,R2 Load Rounded, Long to Short (x) LRER 35 RR R1,R2 Load, Short LER 38 RR R1,R2 Load, Short LE 78 RX R1,D2(X2,B21 Multiply, Extended (x) MXR 26 RR R1,R2 Multiply, Long MDR 2C RR R1,R2 Multiply, Long MD 6C RX R1,D2(X2,B2) Multiply, Long/Extended (x) MXDR 27 RR R1,R2 Multiply, Long/Extended (x) MXD 67 RX R1,D2(X2,B2) Multiply, Short MER 3C RR R1,R2 Multiply, Short ME 7C RX R1,D2(X2,B2) Store, Long STD 60 RX R1,D2(X2,B2) Store, Short STE 70 RX R1,D2(X2,B2) Subtract Normalized, Extended (c,x) SXR 37 RR R1,R2 Subtract Normalized, Long (c) SDR 2B RR R1,R2 Subtract Normalized, Long (c) SO 6B RX R1,D2(X2,B2) Subtract Normalized, Short (c) SER 3B RR R1,R2 Subtract Normalized, Short (c) SE 7B RX R 1,D2(X2,B2) Subtract Unnormalized, Long (c) SWR 2F RR R1,R2 Subtract Unnormalized, Long (c) SW 6F RX R1,D2(X2,B2) Subtract Unnormalized, Short (c) SUR 3F RR R1,R2 Subtract Unnormalized, Short (c) SU 7F RX R1,D2(X2,B2}
EXTENDED MNEMONIC INSTRUCTIONSt Extended Code* Machine Instr.* Use (RX or RR) Meaning (RX or RR)
General B or BR Unconditional Branch BC or BCR 15, NOP or NOPR No Operation BC or BCR 0, After BH or BHR Branch on A High BC or BCR 2, Compare BL orBLR Branch on A Low BCor SCR 4, Instructions BE orBER Branch on A Equal B BC or SCR 8, (A:BI BNH orBNHR Branch on A Not High BC or BCR 13, BNL or BNLR Branch on A Not LQw BC or BCR 11, BNE or BNER Branch on A Not Equal B BC or BCR 7, After BO orBOR Branch on Overflow BC or BCR 1, Arithmetic BP orBPR Branch on Plus BC or BCR 2, Instructions BM orBMR Branch on Minus BC or BCR 4, BNPorBNPR Branch on Not Plus BC or BCR 13, BNM orBNMR Branch on Not Minus BC or BCR 11, BNZorBNZR Branch on Not Zero SCor SCR 7, BZ or BZR Branch on Zero BC or BCR 8, After Test BO orBOR Branch if Ones BC or SCR 1, under Mask BM orBMR Branch if Mixed BC or BCR 4, Instruction BZ or BZR Branch if Zeros BC or BCR 8, BNO orBNOR Branch if Not Ones BC or BCR 14, tSource: GC33-401 0; for ·Second operand, not shown, is D2(X2,B2) OSIVS,VM/370 and DOSIVS. for R
X format and R2 for R
R
format. SOME EDIT AND EDMK PATTERN CHARACTERS (in hex) 20-digit selector 40-blank 5C-asterisk
21-start of significance 4B-period 6B-comma
22-field separator 5B-dollar sign C3D9-CR

CONDITION CODES 0 Condition Code Setting 0 1 2 3
Mask Bit Value 8 4 2 1
General Instructions Add, Add Halfword zero <zero >zero overflow
Add Logical zero, not zero, zero, not zero,
no carry no carry carry carry
AND zero not zero
Compare, Compare Halfword equal 1st op low 1st op high
Compare and Swap/Double equal not equal
Compare Logical equal 1st op low 1st op high
Exclusive OR zero not zero I nsert Characters under Mask all zero 1st bit one 1st bit zero
Load and Test zero <zero >zero
Load Complement zero <zero >zero overflow
Load Negative zero <zero
Load Positive zero >zero overflow
Move Long count equal count low count high overlap OR zero not zero Shift Left Double/Single zero <zero >zero overflow Shift Right Double/Single zero <zero >zero Store Clock set not set error not oper Subtract, Subtract Halfword zero <zero >zero overflow
Subtract Logical not zero, zero, not zero,
no carry carry carry
Test and Set zero one
Test under Mask zero mixed ones
Translate and Test zero incomplete complete
Decimal Instructions Add Decimal zero <zero >zero overflow
Compare Decimal equal 1st op low 1st op high
Edit, Edit and Mark zero <zero >zero Shift and Round Decimal zero <zero >zero overflow
Subtract Decimal zero <zero >zero overflow Zero and Add zero <zero >zero overflow
Floating-Point Instructions Add Normalized zero <zero >zero
Add Unnormalized zero <zero >zero
Compare equal 1st op low 1st op high
Load and Test zero <zero >zero
Load Complement zero <zero >zero
Load Negative zero <zero
Load Positive zero >zero
Subtract Normalized zero <zero >zero
Subtract Unnormalized zero <zero >zero Input/Output Instructions Clear I/O no oper in CSW stored chan busy not oper
progress
Halt Device interruption CSW stored channel not oper
pending working
Halt I/O interruption CSW stored burst op not oper
pending stopped Start I/O, SIOF successful CSW stored busy not oper Store Channel I D ID stored CSW stored busy not oper
Test Channel available interruption burst mode not oper
pending
Test I/O available CSW stored busy not oper
System Control Instructions Load Real Address translation ST entry PT entry length
available invalid invalid violation
Reset Reference Bit R=O,C=O R=O, C=1 R=1, C=O R=1,C=1 Set Clock set secure not oper Signal Processor accepted stat stored busy not oper CNOP ALIGNMENT DOUBLEWORD WORD I WORD HALFWORD I HALFWORD I HALFWORD I HALFWORD
BYTE BYTE I BYTE I BYTE I BYTE • BYTE I BYTE • BYTE 0,8 2,8 4,8 6,8