CF Field
CG Field
CY Field
CD
=
IIII
(I)
This specifies the I register as the destination for the ALU output.
This field controls the ALU-A register entry for High-Low 4 bit gating
and straight crossed switching.
CF
=
0000 (0)
This specifies the ALU-A register entry will be blocked and forced to
zeros. (See example lOA, page 26.)
CF
=
0001 (L)
This specifies the ALU-A register entry Low 4 bits will be gated and the
High 4 bits will be blocked and forced to zeros. (See example lOA, page 26.)
OF
~
0010 (H)
This specifies the ALU-A register entry High 4 bits will be gated and the
Low 4 bits will be blocked and forced to zeros. (See example lOA, page 26.)
CF
=
0011 (Straight)
This specifies the AL U-A register entry High and Low 4 bits will be gated.
(See example lOA, page 26.)
CF
=
0100 (Stop)
This specifies a machine stop function. The machine stops at the end of the
cycle prior to the microword containing this instruction. The WX register
contains the address of this microword.
OF
=
0101 (XL)
This specifies the ALU-A register entry will cross the High 4 bits into the
Low 4 bits and the Low 4 bits into the High 4 bits. Then it gates the Low 4
bits to the ALU and blocks the High 4 bits, forcing them to zeros. (See ex-
ample lOB, page 26.)
CF
=
0110 (XH)
This specifies the ALV-A register entry will cross the High 4 bits into the
Low 4 bits and the Low 4 bits into the High 4 bits.
It
then gates the High 4
bits to the ALU and blocks the Low 4 bits, forcing them to zeros. (See ex-
ample lOB, page 26.)
CF
=
0111 (X)
This specifies the ALU-A register entry will cross the High 4 bits into the
Low 4 bits and the Low 4 bits into the High 4 bits. Then both the High and
Low 4 bits are gated to the ALU. (See example lOB, page 26.)
This field controls the ALU-B entry High-Low 4 bit gating.
CG
=
0000 (0)
This specifies the ALU-B register entry will be blocked and forced to
zeros. (See example 11, page 27.)
CG
=
0001 (L)
This specifies the ALU-B register entry Low 4 bits will be gated, and the
High 4 bits will be blocked and forced to zeros. (See example 11, page 27.)
CG
=
0010 (H)
This specifies the ALU-B register entry High 4 bits will be gated, and the
Low 4 bits will be blocked and forced to zeros. (See example 11, page 27.)
This field controls the ALU true-complement and binary-decimal functions.
CY
=
0000
(+)
This specifies a true binary add.
IBM Con/iJentitll
11

CC
Field
C5
Field
12
IBM COllfidClltill/
CV
=
0001 (-)
This specifies a complement binary add. The B register data is comple-
mented at the ALD-B register entry.
CV
=
00 I 0 (+ 2)
This specifies a binary add under true-complement control. This is de-
pendent on the SO bit which is the true-complement latch.
SO
=
0-True add.
SO
=
I-Complement add.
CV
=
00 I I 3)
This specifies a decimal add under true-complement control. This is de-
pendent on the SO bit which is the true-complement latch.
SO 0-True add.
SO
=
I-Complement add.
This field controls the carry inputs and outputs of the ALD and the logic
functions (AND, OR, XOR).
CC = 0000 (0)
This decode specifies that the carry-input line is to be 0 and ignores the
carry out of the ALD.
CC
=
0001
(II
This decode specifies that the carry-input line is to be 1, and ignores the
carry out of the ALD. (See example I2A, page 27.)
CC
=;=
00 I 0 (.)
This decode specifies the AND function and ignores the carry out of the
ALD. The AND function requires a coincidence of bits to obtain an output.
(See example I2B, page 27.)
CC
=
0011 (0)
This decode specifies the OR function and ignores the carry out of the ALD.
The OR function requires a bit on either side to obtain an output. (See ex-
ample I2C, page 28.)
CC
=
0100 (0 C)
This decode specifies that the carry-input line is to be 0 and sets the S3 bit
to 1 if a carry results. The S3 bit is the carry latch. (See example I2D,
page 28.)
CC
=
0 I 0 I (I C)
This decode specifies that the carry-input line is to be 1 and sets the S3 bit
to 1 if a carry results. The S3 bit is the carry latch.
CC
=
0110 (C C)
This decode specifies the value of the carry latch onto the carry-input line
. and sets the S3 bit to 1 if a carry results. The S3 bit is the carry latch. (See
example I2E, page 28.)
CC = 0111 (V)
This decode specifies the XOR (Exclusive OR) function and ignores the
carry out of the ALD. The XOR function requires no coincidence of bits
to obtain an output. (See example I2F, page 28.)
This field controls the individual sets and resets of status in the S register.
It
also controls some I/O lines. CS has an alternate decoder activated by
the bit AS
=
1.
C5 = 0001
(LZ~
55)
This specifies that if the Low 4 bits of the Z buss are zeros, the S register
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