- -- ---
Add (c) AR lA RR Rl,R2 - - - ---
Add (c) A 5A RX Rl,02(X2,B2) ---_. -
Add Decimal (c) AP FA SS 01 (L l,Bl ),02(L2,B2) Summary
Add Halfword (c) AH 4A RX Rl,02(X2,B2) Add Logical (c) ALR lE RR Rl,R2 Add Logical (c) AL 5E RX R l,02(X2,B2) AND (c) NR 14 RR Rl,R2 AND (c) N
54 RX Rl,02(X2,B2) AND (c) NI 94 SI 01(Bl),12 AND (c) NC 04 SS OHL,Bl),02(B2) Branch and Link BALR 05 RR Rl,R2 Branch and Li n k BAL 45 RX Rl.02(X2.B2) Branch on Condition BCR 07 RR Ml.R2 Branch on Condition BC 47 RX Ml,02(X2,B2) Branch on Count BCTR 06 RR Rl,R2 Branch on Count BCT 46 RX Rl,02(X2,B2) Branch on Index High BXH 86 RS R l,R3.02(B2) Branch on Index Low or Equal BXLE 87 RS R l,R3.02(B2) Clear I/O (c,p) CLRIO 9001 S 02(B2) Compare (c) CR 19 RR Rl,R2 Compare (c) C
59 RX Rl,02(X2.B2) Compare and Swap (c) CS BA RS Rl,R3,02(B2) Compare Decimal (c) CP F9 SS 01 (L 1 ,Bl ),02(L2,B2) GX20-1850-3 Compare Double and Swap (c) COS BB RS Rl,R3,02(B2) Compare Halfword (c) CH 49 RX R l,02(X2,B2) Compare Logical (c) CLR 15 RR Rl,R2 Fourth Edition (November 1976)
Compare Logical (c) CL 55 RX Rl,02(X2,B2) Compare Logical (c) CLC 05 SS 01lL,Bll,02{B2) This reference summary is a minor revision and does not obsolete
Compare Logical (c) CLI 95 SI 01(Bl),12 Compare Logical Characters CLM BO RS Rl,M3,02(B2) the previous edition. Changes include the addition of some new
under Mask (c) DASD and 3203 printer commands, the EBCPIC control
Compare Logical Long (c) CLCL OF RR Rl,R2 characters GE and R
LF, and minor editorial revisions. Convert to Binary CVB 4F RX Rl,02(X2,B2) Convert to Decimal CVO 4E RX Rl,02(X2,B2) The card is intended primarily for use by S/370 assembler lan- (p) 83 Model-dependent
guage application programmers. It contains basic machine in-Divide DR 10 RR Rl,R2 formation on Models 115 through 168 summarized from the Divide 0 50 RX Rl,02(X2,B2) System/370 Principles of Operation (GA22-7000-4), frequently Divide Decimal OP FO SS 01 (L l,Bl ),02(L2,B2) used information from the VS and VM assembler language
Edit (c) ED DE SS 01 (L,Bl ),02(B2) manual (GC33-4010), command codes for various I/O devices,
Edit and Mark (c) EOMK OF SS 01 (L,Bl ),02(B2) and a multi-code translation table. The card will be updated from Exclusive OR (c) XR 17 RR Rl,R2
time to time. However, the above manuals and others cited on the
Exclusive OR (c) X 57 RX R l,02(X2,B2) card are the authoritative reference sources and will be first to Exclusive OR (e) XI 97 SI 01(Bl),12 reflect changes.
Exclusive OR (c) XC 07 SS 01 (L,BlI,02(B2) Execute EX 44 RX Rl,02(X2,B2) Halt I/O (c,p) HIO 9EOO S 02(B2) To distinguish them from instructions carried over from S/360, the Halt Device (c,p) HOV 9EOl S 02(B2) names of instructions essentially new with S/370 are shown in italics. I nsert Character IC 43 RX Rl,02(X2,B2) Some machine instructions are optional or not available for some Insert Characters under Mask (c) ICM BF RS Rl,M3,02(B2) models. For those that are available on a particular model, the user Insert PSW Key (pI IPK B20B S is referred to the appropriate systems reference manual. For a Insert Storage Key (p) ISK 09 RR Rl,R2 particular installation, one must ascertain which optional hardware
Load LR 18 RR Rl,R2 features and programming system(s) have been installed. The
Load L 58 RX Rl,02(X2,B2) floating-point and extended floating-point instructions, as well as
Load Address LA 41 RX R l,02(X2,B2) Load and Test (c) LTR 12 RR Rl,R2 the instructions listed below, are not standard on every model.
Load Complement (c) LCR 13 RR Rl,R2 Monitoring (the MC instruction) is not available on the Model 165,
Load Control (p) LCTL B7 RS Rl,R3,02(B2) except by field installation on purchased models.
Load Halfword LH 48 RX Rl,02(X2,B2) Load Multiple LM 98 RS Rl,R3,02(B2) Conditional swapping CDS, CS Load Negative (c) LNR 11 RR Rl,R2 CPU timer and clock comparator SCKC, SPT, STCKC, STPT Load Positive (c) LPR 10 RR Rl,R2 Direct control RDD,WRD Load PSW (n,p) LPSW 82 S 02(B2) Dynamic address translation LRA, PTLB, RRB, STNSM, Load Real Address (c,p) LRA Bl RX R l,02(X2,B2) STOSM Monitor Call MC AF SI 01(Bl),12 Input/output CLRIO,SIOF Move MVI 92 SI 01(B1),12 Multiprocessing SIGP, SPX, STAP, STPX Move MVC 02 SS 01 (L,Bl ),02(B2) PSW key handling IPK,SPKA Move Long (c) MVCL OE RR Rl,R2 Move Numerics MVN 01 SS 01(L,Bl ),02(B2) Comments about this publication may be sent to the address
Move with Offset MVO Fl SS 01 (L l,Bl ),02(L2,B2) Move Zones MVZ 03 SS 01 (L,Bl ),02(B2) below. All comments and suggestions become the property of IBM. Multiply MR lC RR Rl,R2 Multiply M 5C RX Rl,02(X2,B2) Multiply Decimal MP FC SS 01 (L l,Bl ),02(L2,B2) Multiply Halfword MH 4C RX Rl,02(X2,B2) IBM Corporation, Technical Publications/Systems, Dept. 824, OR (c) OR 16 RR Rl,R2 1133 Westchester Avenue, White Ptains, "N.Y. 10604.
MACHINE INSTRUCTIONS (Contd) OP FOR· ® FloatinltPoint Instructions (Contd) OP FOR· 0 NAME MNEMONIC CODE MAT OPERANDS NAME MNEMONIC CODE MAT OPERANDS OR (c) 0 56 RX R1.02(X2.B2) Compare. Long Ic) CDR 29 RR R1.R2 OR (c) 01 96 SI 01(B1),12 Compare, Long (c) CD 69 RX R1,021X2,B2) OR (c) OC 06 SS 011L,Bll,02(B2) Compare, Short (c) CER 39 RR R1,R2
Pack PACK F2 SS 01 (L 1,B1 ),D2(L2,B2) Compare, Short (c) CE 79 RX R
Purge TLB (p) PTLB B200 S Divide, Long ODR 20 RR R1,R2
Read Direct (p) ROD 85 SI 01(B1),12 Divide, Long DO 60 RX R1,021X2,B2) Reset Reference Bit (c,p) RRB B213 S 02(B2)
Divide, Short OER 3D RR R1,R2 Set Clock (c,p) SCK B204 S 02(B2)
Divide, Short DE 70 RX R1,02(X2,B2)
Set Clock Comparator (p) SCKC B206 S 02(B2) Halve, Long HOR 24 RR R1,R2 Set CPU Timer (p) SPT B208 S 02(B2) Halve, Short HER 34 RR R1,R2 Set Prefix (p) SPX B210 S D2(B2)
Load and Test, Long Ic) LTDR 22 RR R1,R2 Set Program Mask (n) SPM 04 RR R1
Load and Test, Short (c) LTER 32 RR R1,R2 Set PSW Key from Address (p) SPKA B20A S 02(B2)
Load Complement, Long (c) LCOR 23 RR R1,R2 Set Storage Key (p) SSK 08 RR R1,R2
Load Complement, Short Ic) LCER 33 RR R1,R2 Set System Mask (p) SSM 80 S 02(B2)
Load, Long LOR 28 RR R1,R2
Shift and Round Decimal (c) SRP FO SS 01 (L 1,B1 ),02(B2),13 Load, Long LO 68 RX R1,02(X2,B2) Shift Left Double (c) SLOA 8F RS R1,D2(B2)
Load Negative, Long (c) LNOR 21 RR R1,R2 Shift Left Double Logical SLOL 80 RS R1,02(B2)
Load Negative, Short (c) LNER 31 RR R1,R2 Shift Left Single (c) SLA 8B RS R1,02(B2)
Load Positive, Long (c) LPOR 20 RR Rl,R2 Shift Left Single Logical SLL 89 RS R1,02(B2)
Load Positive, Short Ic) LPER 30 RR R1,R2 Shift Right Double (c) SROA 8E RS R1,02(B2)
Load Rounded, Extended to Long (x) LROR 25 RR R1,R2 Shift Right Double Logical SROL 8C RS R1,02(B2)
Load Rounded, Long to Short (x) LRER 35 RR R1,R2 Shift Right Single (c) SRA 8A RS R1,02(B2)
Load, Short LER 38 RR R1,R2 Shift Right Single Logical SRL 88 RS R1,02(B2)
Load, Short LE 78 RX R1,02(X2,B21 Signal Processor (c,p) SIGP AE RS R1,R3,D2(B2)
Multiply. Extended (x) MXR 26 RR R1,R2 Start I/O (c,p) SIO 9COO S 02(B2)
Multiply, Long MOR 2C RR R1,R2
Start I/O Fast Release (c,p) SIOF 9C01 S 02(B2)
Multiply, Long MD 6C RX R1,02(X2,B2) Store ST 50 RX R
1 ,02(X2,B2)
Multiply, Long/Extended (x) MXOR 27 RR R1,R2
Store ChannellD (c,p) STIOC B203 S 02(B2)
Multiply, Long/Extended (x) MXD 67 RX R1,02(X2,B2) Store Character STC 42 RX R1,02(X2,B2)
Multiply, Short MER 3C RR R1,R2
Store Characters under Mask STCM BE RS R1,M3,D2(B2)
Multiply. Short ME 7C RX R1.02(X2,B2)
Store Clock (c) STCK B205 S 02(B2) Store, Long STO 60 RX R1,D2(X2,B2)
Store Clock Comparator (p) STCKC B207 S D2(B2) Store. Short STE 70 RX R1,02(X2,B2)
Store Control (p) STCTL B6 RS R1.R3,02(B2)
Subtract Normalized, Extended (c,x) SXR 37 RR R1,R2
Store CPU Address (p) STAP B212 S 02(B2) Subtract Normalized, Long (c) SOR 2B RR R1,R2
Store CPU ID (p) STIOP B202 S 02(B2) Subtract Normalized, Long (c) SO 6B RX R1,02(X2,B2)
Store CPU Timer (p) STPT B209 S 02(B2) Subtract Normalized, Short Ic) SER 3B RR R1,R2 Store Halfword STH 40 RX R
1,02(X2,B2) Subtract Normalized, Short Ic) SE 7B RX R
1 ,D2IX2,B2) Store Multiple STM 90 RS R1.R3,D2(B2) Subtract Unnormalized, Long (c) SWR 2F RR R1,R2
Store Prefix (p) STPX B211 S 02(B2) Subtract Unnormalized, Long (c) SW 6F RX R1,02(X2,B2)
Store Then AND System STNSM AC SI 01 (B1),12 Subtract Unnormalized, Short (c) SUR 3F RR R1,R2 Mask (p) Subtract Unnormalized, Short Ic) SU 7F RX R1,02(X2,B2)
Store Then OR System Mask Ipl STOSM AD SI 01(B1),12 Subtract (c) SR 1B RR R1,R2
Extended Code * Machine Instr. * Subtract Decimal (c) SP FB SS 01 (L 1,B1 ),02(L2,B2)
Use (RX or RR) Meaning (RX or RR) Subtract Halfword (c) SH 4B RX R1,02(X2,B2) Subtract Logical Ic) SLR 1F RR R1,R2 General B or BR Unconditional Branch BC or BCR 15, Subtract Logical (c) SL 5F RX R 1,021X2,B2) NOP or NOPR No Operation BC or BCR 0, Supervisor Call SVC OA RR I After BH or BHR Branch on A High BC or BCR 2, Test and Set (c) TS 93 S 02(B2) Compare BL orBLR Branch on A Low BCor SCR 4, Test Channel (c,p) TCH 9FOO S D2(B2)
Instructions SE orBER Branch on A Equal B BC or SCR 8, Test I/O (c,p) TIO 9000 S 02(B2) IA:B) BNH orBNHR Branch on A Not High BC or BCR 13, Test under Mask (c) TM 91 SI 01(B1),12 BNL or BNLR Branch on A Not LQw BC or BCR 11,
Translate TR DC SS 01(L,B1),02(B2)
BNE or BNER Branch on A Not Equal B BC or BeR 7, Translate and Test (c) TRT DO SS 01 (L,B1 ),02(B2)
After BO orBOR Branch on Overflow BC or BCR 1, Unpack UNPK F3 SS 01 (L 1,B1 ),02(L2,B2)
Arithmetic BP orBPR Branch on Plus BC or BCR 2, Write Direct (p) WRO 84 SI 01lB1),12 Instructions BM orBMR Branch on Minus BC or BCR 4, Zero and Add Decimal (c) ZAP F8 SS 01 IL 1,B1 ),02(L2,B2)
BNPorBNPR Branch on Not Plus BC or BCR 13, BNM orBNMR Branch on Not Minus BC or BCR 11, FloatinltPoint Instructions BNZorBNZR Branch on Not Zero BCor SCR 7, DP FOR· BZ or BZR Branch on Zero BC or BCR 8, NAME MNEMONIC CODe MAT OPERANDS After Test BO orBOR Branch if Ones BC or SCR 1, Add Normalized, Extended (c,x) AXR 36 RR R1,R2
under Mask BM orBMR Branch if Mixed BC or BCR 4, Add Normalized, Long (c) AOR 2A RR R1,R2
Instruction BZ or BZR Branch if Zeros BC or BCR 8, Add Normalized, Long Ic) AD 6A RX R1,02(X2,B2) BNO orBNOR Branch if Not Ones BC or BCR 14,
Add Normalized, Short (c) AER 3A RR R1,R2
Add Normalized, Short Ic) AE 7A RX R
1,02(X2,B2) tSource: GC33-401 0; for ·Second operand, not shown, is D2(X2,B2)
Add Unnormalized, Long (c) AWR 2E RR R1,R2 OSIVS,VM/370 and DOSIVS. for R
X format and R2 for R
Add Unnormalized, Long (c) AW 6E RX R1,02IX2,B2) Add Unnormal'ized, Short Ic) AUR 3E RR R1,R2 SOME EDIT AND EDMK PATTERN CHARACTERS (in hex) Add Unnormalized, Short (c) AU 7E RX R1,D2(X2,B2)
20-digit selector 40-blank 5C-asterisk
c. Condition code is set. p. Privileged instruction.
21-start of significance 4B-period 6B-comma
n. New condition code is loaded. x. Extended precision floating-point.
22-field separator 5B-dollar sign C309-CR
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