Chapter 4. Shadow-Table-Bypass Assist
The shadow-table-bypass assist enhances the pertDrmance-uf virttrai--ma:chines virtual = real option is specified in Virtual Machine
Facility/370 (VM/370) pro-gram pl"oducts. VM/370 normally employs shadow tables for
virtual machines operating in the Ee mcOde with DAY on. Shadow tables are segment tables and page tables. used by the dynamic-address,. translation (DAT) facility of thereallllachine for
direct translation of logical addresses of the virtual machine to real addressesQf -the real machine. For
machines with the virtual=-real option, however,
most addresses translated through the shadow tables give the same result as if they were
translated only through the virtual-:-.tnachine translation tables. Two specific techniques are used. in different to exploit this character.istic of the. shadow tables of machines having the virtual = real option.
1. In the true shadow-table-bypass technique, the
virtual,..machine segment and page tables are
used directly by the real-machine DAT
mechanism. Hence, no distinct shadow tables
exist, and the virtual-machine-segment table
origin and length are used wherever the general VM/370 design calls for the values of the
shadow segment-table origin and length. because the VM/370 does not map
the first 4K bytes of the virtual-machine
storage to the first 4K bytes of real storage, this
technique requires that those page-table entries
of the virtual machine which refer to the first
4K bytes be modified by VM/370 so that this
remapping can be accomplished without
separate shadow tables.
2. In the single-processor-mode technique used for
a virtual = real virtual machine running MVS, 253 of the 256 page tables of the virtual
machine are used directly, and only three of the
page tables of the virtual machine have distinct
counterpart shadow page tables. The shadowed
tables are the tables that contain some entry
having a real page-frame address for which
prefixing or reverse prefixing of the virtual
machine applies. Thus, single-processor mode
is only a partial bypass of the shadow tables. A
separate shadow segment table is maintained,
253 of whose entries refer directly to virtual
page tables in the storage of the virtual
machine.
The shadow-table-bypass assist improves
performance of certain virtual machines having the
virtual = real option by executing seven specific
virtual-machine instructicns and one type of virttlal-maehine pro-g-l"amint€l":}"uptiondirectiy without requiring any intervention or assistance by
the VM/370 control program.
The assisted instructions are:
INVALIDATE PAGE TABLE ENTRY LOAD CONTROL LOAD REAL ADDRESS PURGE TLB STORE THEN AND SYSTEM MASK STORE THEN OR SYSTEM MASK TEST PROTECTION The virtual-machine program interruption is for
page-fault reflection and consists in taking a
program interruption for a page-translation
condition directly in the virtual machine.
Relation of Shadow-Table-Bypass
Assist to Other Assists
The shadow-table-bypass assist (STBA) is related
to the virtual-machine assist (VMA) and to the
expanded virtual-machine assist (EVMA) which is
part of ECPS:VM/370. All three assists use bits 0, 1, 3, 5, and 8-28 of control register 6 as follows:
Bit Meaning
o When the bit is zero, assists are inactive; when
the bit is one, VMA is active; when it is one
and bit 6 of control register 6 is one, EVMA is
active; when it is one and bit 8 of the assist
control word is one, STBA is active.
1 Virtual-machine problem-state bit.
3 When the bit is zero, only operation codes for System/370 are assisted.
5 \Vheil the bit is one, shadow-table validation is
active; when it is zero, the page-fault-reflection
function is performed if bits 8 and 11 of the
assist control word are both ones.
8-28 Bits 8-28 are bits 8-28 of the address of the
virtual-machine parameter list (MICBLOK)
aligned on a doubleword boundary.
In addition, these assists use the following words
of the virtual-machine parameter list: Offset (Hex) Field Symbol Use 0 MICRSEG Real segment-table address
4 MICCREG Address of ECBLOK
8 MICVPSW Address of virtual PSW bits 0-15 14 MICACF Assist control word
None of the eight functions of the shadow­
table-bypass assist is active unless (1) bit 0 of
control register 6 is one, (2) bit 8 of the assist
control word is one, and (3) a specific bit of bits
9-15 of the assist control word is one. The specific
activation bit depends on the function. (See Figure
22.) Six bits are used for eight functions. Each bit
Shadow-Tabie-Bypass Assist 31

. ¢ \1M Po, L r kuc.& ? rct;,\[ J.-' Bits 0-5 Bits 8-15 of 2.. of Control Assist 3 ... 1' Function Register 6 Control Word
4 t \I c... '!../\.Y\ J Invalidate page table entry 10XO XX lXlX XXXX r.:" S \JcJ- ,-··,'·v< J I Load control 10XO XX I lXXX XXXl I :- /'. i".. f"J A"', 1 if" 1 't.!(i. r H (/",;/\.1:'('\.:1-, Load real address 10XO XX lXXX lXXX .f \J:=c 1:-. &".4.{0\ '2.'1 \1M E\=" r;. :':.. . Purge TLB 10XO XX l1XX XXXX Store then AND system mask 10XO XX lXXX XX1X .. /1, 3. L?f' II (" A s, " Store then OR system mask 10XO XX lXXX XX1X f:.,(r 2. ¢ MoO<; f. 1-" (:T:;:\,FL ...... '''1 1''''CU5 CbN\l?21L Test protection 10XO XX lX1X XXX X 'L -rPPT (Q I\VR 21 L .3 v-r:«"Tof'tL 2A&12 i-,Ll0LT Page-fault reflection lXXX XO lXXl
Figure 22. Bits That Activate STBA Functions
activates a single function, except that bit 10 controls INVALIDATE PAGE TABLE ENTRY and TEST PROTECTION and bit 14 controls STORE THEN AND SYSTEM MASK and STORE THEN OR SYSTEM MASK. Additional conditions
must be satisfied to activate each function. The
additional conditions are given in the descriptions
of the individual assist functions.
The shadow-table-bypass assist is logically
independent of the virtual-machine assist. For the
most part, the two assists complement each other.
However, when the load-real-address function of
the STBA is installed and active, and the VMA is
also installed, the load-real-address function of
STBA overrides that of the VMA. The expanded
virtual-machine assist is effective when the other
two assists, though active, are not applicable.
INVALIDATE PAGE TABLE
ENTRY
The INVALIDATE PAGE TABLE ENTRY instruction is executed for a virtual machine if the
corresponding function of the shadow-table-bypass
assist is activated, unless (1) the virtual machine is
not in the EC mode with DAT on and the
problem-state bit zero, (2) some pertinent VM/370 control field cannot be fetched, or (3) the entry to
be invalidated is in the first 4K-byte locations in
virtual storage.
The invalidate-page-table-entry (IPTE) function
of the shadow-table-bypass assist is invoked each
time a CPU attempts to execute an INV ALIDA TE PAGE TABLE ENTRY instruction when the
problem-state bit of the real CPU is zero.
Execution of this function consists in performing
the following steps:
32 Virtual-Machine Assist and Shadow-Table-Bypass Assist
XXXX
4 L-v:I\ COI\.\Te21L S h,) LL S,9T CDf'.{-:-:-e.6 . b ,Si,;as.M + L-UL. 1. If bits 0-3 of control register 6 are not lOXO binary, a program interruption takes place for a
privileged-operation exception, and execution
of this IPTE instruction is suppressed (I.A.I).
2. The assist control word, MICACF, is fetched
with a key of zero. Execution ends if an
addressing condition is encountered (l.A.2).
3. Execution ends with a program interruption for
a privileged-operation exception if bits 8 and IO of the assist control word are not both ones
(1.A.3).
4. MICVPSW, which contains the address of the
virtual PSW, is fetched with a key of zero.
Execution ends if an addressing condition is
encountered (l.A.4)
5. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution ends if an addressing
condition is encountered (l.A.5).
6. Execution ends with a program interruption for
a privileged-operation exception if bits 5 and
12 of the virtual PSW are not both ones (that
is, if the virtual machine is not in the EC mode
with DAT on) (I.A.6).
7. If an access condition is encountered in
fetching the second halfword of the IPTE
instruction, execution of this function ends, and
a program interruption takes place for the
access exception encountered (I.B).
8. The address of the page-table entry is
computed by using the page-table-origin value
from the general register specified by the R I
field and the page index from the address in the
general register specified by the R2 field. Bits
8-12 of real control register 0 determine the bit
positions that contain the page-index value. A
program interruption takes place for a
privileged-operation exception if the computed