8. The effective address is translated, and a
condition-code value is derived just as if LRA
were being executed with the real problem-state
bit set to zero. If a translation specification or actclfes-sing conditton -is-encountel ed, execution
of this function ends with the occurrence of a
program interruption for the exception
encountered; otherwise, the translated address
is placed in the general register specified by the
R 1 field of the instruction, and the condition
code is set. Execution of this function then
ends, with execution of LRA completed (2).
Figure 25 summarizes the fields used.
PURGETLB
The PURGE TLB instruction is executed for a
virtual machine if the corresponding function of the
shadow-table-bypass assist is active, unless (1) a
virtual-machine-exception condition is recognized
or (2) some pertinent VM/370 control field cannot
be accessed.
The TLB (PTLB) function of the
shadow-table-bypass assist is invoked each time a CPU attempts to execute a PURGE TLB
instruction when the problem-state bit of the real PSW is one. Execution of this function consists in
performing the following steps:
1. If bits 0-3 of control register 6 are not 10XO binary, a program interruption takes place for a
privileged-operation exception, and execution
of the PTLB instruction is suppressed (I.A.l).
2. The assist control word, MICACF, is fetched
with a key of zero. Execution ends if an
addressing condition is encountered (l.A.2).
3. Execution ends if bits 8 and 9 of the assist
control word are not both ones. If execution of
this function is ended, the purge-TLB function
of the expanded virtual-machine assist is
invoked when that assist is installed. When
Field Control Address Offset No. of
Name Block Type (Hex) Bytes Contents
that assist is not installed, the ending of
execution of this function results in a program
interruption for a privileged-operation
exception (1.A.3).
4. if-an-access-condition-is- encountered-in-­ fetching the second halfword of the PTLB
instruction, it is unpredictable whether this
condition is ignored, because no information is
needed from that halfword to execute the
instruction. If an access condition is
encountered and is not ignored, execution of
this function ends, and a program interruption
takes place for that access exception (1.B). Steps 5 through 7 mayor may not be performed
on a CPU which is not configured in a two-CPU configuration.
5. The APST A T 1 byte is fetched with a key of
zero from reallocation 69A hex. Execution
ends if an addressing condition is encountered
(2).
6. The CPPTLB bit (bit 6) of APSTAT2 in the PSA of the CPU executing the purge-TLB
function is set to zero (3).
7. If the APUOPER bit (bit 0) of APSTATI is
zero, indicating that no attached processor is
operational, this step is complete. Otherwise, the PREFIXB word is fetched with a key of
zero from real location 664 hex. The real
address of the APST A T2 byte in the PSA of
the other CPU is computed by adding 69B hex,
right-justified, to the PREFIXB word. The (bit 6) of the byte whose real
address was just computed is set to one with a
key of zero for the storage-access update.
Execution ends if an addressing condition is
encountered (4).
8. The TLB of the CPU executing the function is
purged (5).
Figure 26 summarizes the fields used. MICVPSW MICBLOK Real 8 4 Address of VMPSW MICACF MICBLOK Real 14 4 Assist control word IVMPSW VMBLOK I Rea 1 I 0 I 2 IVirtual PSW bits 0-151 I IOperand 2 1 IVirtuall 0 I 1 ill 1
No operand reference to storage is made; however, the
translation-table references at real addresses are made
as if an operand reference were going to be made. Figure 25. Fields Used in LOAD REAL ADDRESS Shadow-Table-Bypass Assist 35

Field Control Add.ress Offset No. of Name Block Type (Hex), Bytes Contents l MICAtf MJ.CBLOK Real -14 4 As,sist control word PRfFtXB . PSA Real 664 4 Re.al address of PSA of ather CPU APSTATl PSA Real 6_9A 1 Bit 0 S€.t to one indi-
cates attached pro-
cessor operational APSTAT2. PSA Real 69B 1 Bit 6 set to one
indicates PURGE TLB
is requested on
this CPU APSTAT2. PSA of Real 69B 1 Bit 6 set to one
Other indicates PURGE TLB CPU is requested on the other CPU Figure 26. Fields Used in PURGE TLB
Programming Note
When the CPPTLBR bit in the PSA of a CPU is
set to one, the translation-Iookaside buffer of that CPU should be purged before the VM/370 control
program dispatches a different virtual m.achine on
that CPU. This is to ensure that if a virtual
machine that executed a PURGE TLB is later
redispatched on that CPU, any TLB entries left in
that CPU will have been purged.
STORE THEN AND SYSTEM MASK
The STORE THEN AND SYSTEM MASK instruction is executed for a virtual machine if the
corresponding function of the shadow-table-bypass
assist is activated and the instruction uses an 12
field value of FB hex to turn off the DAT bit in the
virtual PSW. The store-then-AND-system-mask (STNSM) function of the shadow-table-bypass assist is
invoked each time a CPU attempts to execute a STORE THEN AND SYSTEM MASK instruction
when the problem-state bit of the real PSW is one.
Execution of this function consists in performing
the following steps:
1. If bits 0-3 of control register 6 are not 10XO binary, a program interruption takes place for a
privileged-operation exception, and execution
of the STNSM instruction is suppressed
(l.A.1).
2. MICVPSW, which contains the address of the
virtual PSW, is fetched with a key of zero.
Execution ends if an addressing condition is
encountered (1.A.2).
36 Virtual-Machine Assist and Shadow-Table-Bypass Assist
3. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution ends if an addressing
condition is encountered (l.A. 3).
4. Execution of this function ends if bit 12 of the
virtual PSW is zero. Ending consists in
invoking the STNSM function of the virtual­
machine assist if that assist is installed;
otherwise, the STNSM function of the
expanded virtual-machine assist is invoked. If
neither assist is installed, a program
interruption for a privileged-operation
exception takes place (l.A.4).
S. Execution of this function ends if the second
operand is not FB hex. Ending consists in
invoking the STNSM function of the virtual­
machine assist if that assist is installed;
otherwise, the STNSM function of the
expanded virtual-machine assist is invoked. If
neither assist is installed, a program
interruption for a privileged-operation
exception takes place (l.A.S).
6. The assist-control word, MICACF, is fetched
with a key of zero. Execution ends if an
addressing condition is encountered (1.A.6).
7. If bits 8 and 14 of the assist control word are
not both ones, execution of this function ends.
Ending consists in invoking the STNSM
function of the virtual-machine assist if that
assist is installed; otherwise, the STNSM function of the expanded virtual-machine assist
is invoked. If neither assist is installed, a
program interruption for a privileged-operation
exception takes place (1.A. 7).
8. If an access condition is encountered in
fetching the second halfword of the STNSM