January 19952
Philips SemiconductorsProduct specification
Quadruple bilateral switches
HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to V
DD a low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to V
SS the switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram.Fig.2 Pinning diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
• Analogue and digital switching
E
0 to E
3 enable inputs
Y
0 to Y
3 input/output terminals
Z
0 to Z
3 input/output terminals
Fig.3 Schematic diagram (one switch).

January 19953
Philips SemiconductorsProduct specification
Quadruple bilateral switches
HEF4066B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC134)
DC CHARACTERISTICS
T
amb =2 5C
Power dissipation per switchPmax.100mW
For other RATINGS see Family Specifications
V
DD
V
SYMBOL MIN. TYP . MAX. CONDITIONS
ON resistance
5
R
ON
- 350 2500 W E
n at V
DD
10 - 80 245 W V
is =V
SS to V
DD
15 - 60 175 W see Fig.4
ON resistance
5
R
ON
- 115 340 W E
n at V
DD
10 - 50 160 W V
is =V
SS
15 - 40 115 W see Fig.4
ON resistance
5
R
ON
- 120 365 W E
n at V
DD
10 - 65 200 W V
is =V
DD
15 - 50 155 W see Fig.4
‘ D ’ ON resistance5
D R
ON
- 25 -W E
n at V
DD
between any two10-10-WV
is =V
SS to V
DD
channels 15 - 5 -W see Fig.4
OFF state leakage5
I
OZ
--- nA
E
n at V
SS current, any10---nA
channel OFF15--200nA
E
n input voltage5
V
IL
- 2,25 1 V
I
is =1 0m A
see Fig.9
LOW 10 - 4,50 2 V
15 - 6,75 2 V
V
DD
V
SYMBOL T
amb ( c) CONDITIONS
- 40 +25 +85
MAX. MAX. MAX.
Quiescent device5
I
DD
1,0 1,0 7,5 mAV
SS = 0; all valid
current 10 2,0 2,0 15,0 m A input combinations;
15 4,0 4,0 30,0 mAV
I =V
SS or V
DD
Input leakage current at E
n 15 – I
IN - 300 1000 nA E
n at V
SS or V
DD