page-table address is less than 4096. On some
models, this interruption also takes place when
the page-table origin is less than 4096 (2).
9. This function invalidates a page-table entry just
-as ufliel1\tVJtt;m-A.-'fE--¥AGE--'fABE-E-----­ ENTRY instruction were executed with the
problem-state bit set to zero. In particular,
certain entries in the translation-Iookaside
buffer of all configured CPUs must be purged.
If a protection or addressing exception is
encountered, a program interruption for
protection or addressing takes place in the
normal manner (3).
Figure 23 summarizes the fields used.
Programming Notes
1. IPTE is not assisted if the page-table entry is in
the first 4K bytes of real storage because
VM/3 7 0 does not map that storage as virtual
equals real.
2. A translation-specification exception for a
format error in bits 8-12 of real control register
o cannot arise in executing IPTE under VM/370 because VM/370 always executes
virtual-machine instructions with real DAT on,
and a format error would prevent the fetching
of any virtual-machine instruction. LOAD CONTROL The LOAD CONTROL instruction is executed for
a virtual machine if the corresponding function of
the shadow-table-bypass assist is activated; the
instruction loads virtual control register 1 only
when the virtual machine is in the EC mode with
DAT on.
The load-control function of the shadow-table­
bypass assist is invoked each time a CPU attempts
to execute a LOAD CONTROL instruction when
the problem-state bit of the real PSW is one. The
execution of this function consists in performing
the following steps:
1. If bits 0-3 of control register 6 are not 10XO binary, a program interruption takes place for a
privileged-operation exception, and execution
Field Control Address Offset No. of
Name Block Type (Hex) Bytes Contents of the LOAD CONTROL instruction is
suppressed (I.A.l)". 2. The assist control word, MICACF, is fetched
with a key of zero. Execution ends if an (l.A.2.A.I).
3. Execution ends with a program interruption for
a privileged-operation exception if bits 8 and
15 of the assist control word are not both ones
( l.A.2.A.2).
4. MICVPSW, which contains the address of the
virtual PSW, is fetched with a key of zero.
Execution ends if an addressing condition is
encountered (l.A.2.A.3).
S. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution ends if an addressing
condition is encountered (l.A.2.A.4).
6. Execution ends with a program interruption for
a privileged-operation exception if bits 5 and
12 of the virtual PSW are not both ones (that is, if the virtual machine is not in the BC mode
with DAT on) (l.A.2.A.S).
7. Execution ends with a program interruption for
a privileged-operation exception if the R
J
and
R3 fields of the LOAD CONTROL instruction
are not both one (hex) (1.A.2.B).
8 .. If an access condition is encountered in
fetching the second halfword of the LOAD CONTROL instruction, execution of this
function ends, and a program interruption takes place with that access exception indicated
(l.B).
9. The LOAD CONTROL instruction is executed
just as if the real problem-state bit were If an exception is recognized, execution this function ends, and a program interruption takes place indicating that exception (2). 10. If the value in real control register 1 was .not changed, execution of the LOAD CONTROL instruction is complete (3).
11. MICCREG, the word containing the address of
the ECBLOK control block,is fetched with .a key of zero. Execution of the LOAD CONTROL instruction is terminated, and a IMICVPSW MICBLOK Real I 8 I 4 Address of VMPSW IAssist contral word I 'Virtual PSW bits 0-lS
t
/MICACF VMPSW Operand 2 lMICBLoKIReal VMBLOK Real
Real
14
o
4
2
2 Page-table entry
Figure 23. Fields Used in INVALIDATE PAGE TABLE ENTRY
Shadow-Table-Bypass Assist 33
program interruption takes place if an
addressing exception is recognized (4.A.1).
12. The value in real control register 1 is stored,
with a key of zero, in virtual control register 1,
EXTCR 1. Execution of the LOAD CONTROL instruction is terminated, and a
program interruption takes place if an
addressing exception is recognized (4.A.2.A).
13. The value in real control register 1 is stored,
with a key of zero, in shadow control register
1, EXTSHCRl. Execution of the LOAD CONTROL instruction is terminated, and a
program interruption takes place if an
addressing exception is recognized (4.A.2.B).
14. The value in real control register 1 is stored,
with a key of zero, in RUNCRl, in the real PSA (4.B).
Figure 24 summarizes the fields used.
LOAD REAL ADDRESS
The LOAD REAL ADDRESS instruction is
executed for a virtual machine if the corresponding
function of the shadow-table-bypass assist is
activated, unless (1) a virtual-machine-exception
condition is recognized, (2) some pertinent VM/370 control field cannot be fetched, or (3) the
virtual machine is not in the EC mode with DA T
on.
The load-real-address (LRA) function of the
shadow-table-bypass assist is invoked each time a CPU attempts to execute a LOAD REAL
ADDRESS instruction when the problem-state bit
of the real PSW is one. Execution of this function
consists in performing the following steps:
Field Control Address Offset No. of
Name Block Type (Hex) Bytes Contents MICCREG MICBLOK Real 4 4 Address MICVPSW MICBLOK Real 8 4 Address
1. If bits 0-3 of control register 6 are not 10XO binary, a program interruption takes place for a
privileged-operation exception, and execution
of the LRA instruction is suppressed (I.A.1).
2. The assist control word, MICACF, is fetched
with a key of zero. Execution ends if an
addressing condition is encountered (l.A.2).
3. Execution ends with a program interruption for
a privileged-operation exception if bits 8 and
12 of the assist control word are not both ones.
If execution of this function is ended, the
load-real-address function of the virtual­
machine assist is invoked when the virtual­
machine assist is installed. When the virtual­
machine assist is not installed, the ending of
execution of this function results in a program
interruption for a privileged-operation
exception (l.A.3).
4. MICVPSW, which contains the address of the
virtual PSW, is fetched with a key of zero.
Execution ends if an addressing condition is
encountered (l.A.4).
5. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution ends if an addressing
condition is encountered (l.A.5).
6. Execution ends with a program interruption for
a privileged-operation exception if bits 5 and
12 of the virtual PSW are not both ones (that
is, if the virtual machine is not in the EC mode
with DAT on) (l.A.6).
7. If an access condition is encountered in
fetching the second halfword of the LRA
instruction, execution of this function ends,
and a program interruption takes place for that
access exception (I.B). of ECBLOK of VMPSW MICACF MICBLOK Real 14 4 Assist control word
EXTCRl ECBLOK Real 4 4 Virtual control
register 1 EXTSHCRl ECBLOK Real 44 4 Shadow control
register 1 VMPSW VMBLOK Real 0 2 Virtual PSW bits 0-15
RUNCR1 PSA Real 344 4 Control register
1 atl
dispatch
Operand -Logical -4 New control-register-I
1 value I Figure 24. Fields Used in LOAD CONTROL 34 Virtual-Machine Assist and Shadow-Table-Bypass Assist
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