MACHINE INSTRUCTIONS (Contd) OP FOR· ® FloatinltPoint Instructions (Contd) OP FOR· 0 NAME MNEMONIC CODE MAT OPERANDS NAME MNEMONIC CODE MAT OPERANDS OR (c) 0 56 RX R1.02(X2.B2) Compare. Long Ic) CDR 29 RR R1.R2 OR (c) 01 96 SI 01(B1),12 Compare, Long (c) CD 69 RX R1,021X2,B2) OR (c) OC 06 SS 011L,Bll,02(B2) Compare, Short (c) CER 39 RR R1,R2
Pack PACK F2 SS 01 (L 1,B1 ),D2(L2,B2) Compare, Short (c) CE 79 RX R
1,D2(X2,B2)
Purge TLB (p) PTLB B200 S Divide, Long ODR 20 RR R1,R2
Read Direct (p) ROD 85 SI 01(B1),12 Divide, Long DO 60 RX R1,021X2,B2) Reset Reference Bit (c,p) RRB B213 S 02(B2)
Divide, Short OER 3D RR R1,R2 Set Clock (c,p) SCK B204 S 02(B2)
Divide, Short DE 70 RX R1,02(X2,B2)
Set Clock Comparator (p) SCKC B206 S 02(B2) Halve, Long HOR 24 RR R1,R2 Set CPU Timer (p) SPT B208 S 02(B2) Halve, Short HER 34 RR R1,R2 Set Prefix (p) SPX B210 S D2(B2)
Load and Test, Long Ic) LTDR 22 RR R1,R2 Set Program Mask (n) SPM 04 RR R1
Load and Test, Short (c) LTER 32 RR R1,R2 Set PSW Key from Address (p) SPKA B20A S 02(B2)
Load Complement, Long (c) LCOR 23 RR R1,R2 Set Storage Key (p) SSK 08 RR R1,R2
Load Complement, Short Ic) LCER 33 RR R1,R2 Set System Mask (p) SSM 80 S 02(B2)
Load, Long LOR 28 RR R1,R2
Shift and Round Decimal (c) SRP FO SS 01 (L 1,B1 ),02(B2),13 Load, Long LO 68 RX R1,02(X2,B2) Shift Left Double (c) SLOA 8F RS R1,D2(B2)
Load Negative, Long (c) LNOR 21 RR R1,R2 Shift Left Double Logical SLOL 80 RS R1,02(B2)
Load Negative, Short (c) LNER 31 RR R1,R2 Shift Left Single (c) SLA 8B RS R1,02(B2)
Load Positive, Long (c) LPOR 20 RR Rl,R2 Shift Left Single Logical SLL 89 RS R1,02(B2)
Load Positive, Short Ic) LPER 30 RR R1,R2 Shift Right Double (c) SROA 8E RS R1,02(B2)
Load Rounded, Extended to Long (x) LROR 25 RR R1,R2 Shift Right Double Logical SROL 8C RS R1,02(B2)
Load Rounded, Long to Short (x) LRER 35 RR R1,R2 Shift Right Single (c) SRA 8A RS R1,02(B2)
Load, Short LER 38 RR R1,R2 Shift Right Single Logical SRL 88 RS R1,02(B2)
Load, Short LE 78 RX R1,02(X2,B21 Signal Processor (c,p) SIGP AE RS R1,R3,D2(B2)
Multiply. Extended (x) MXR 26 RR R1,R2 Start I/O (c,p) SIO 9COO S 02(B2)
Multiply, Long MOR 2C RR R1,R2
Start I/O Fast Release (c,p) SIOF 9C01 S 02(B2)
Multiply, Long MD 6C RX R1,02(X2,B2) Store ST 50 RX R
1 ,02(X2,B2)
Multiply, Long/Extended (x) MXOR 27 RR R1,R2
Store ChannellD (c,p) STIOC B203 S 02(B2)
Multiply, Long/Extended (x) MXD 67 RX R1,02(X2,B2) Store Character STC 42 RX R1,02(X2,B2)
Multiply, Short MER 3C RR R1,R2
Store Characters under Mask STCM BE RS R1,M3,D2(B2)
Multiply. Short ME 7C RX R1.02(X2,B2)
Store Clock (c) STCK B205 S 02(B2) Store, Long STO 60 RX R1,D2(X2,B2)
Store Clock Comparator (p) STCKC B207 S D2(B2) Store. Short STE 70 RX R1,02(X2,B2)
Store Control (p) STCTL B6 RS R1.R3,02(B2)
Subtract Normalized, Extended (c,x) SXR 37 RR R1,R2
Store CPU Address (p) STAP B212 S 02(B2) Subtract Normalized, Long (c) SOR 2B RR R1,R2
Store CPU ID (p) STIOP B202 S 02(B2) Subtract Normalized, Long (c) SO 6B RX R1,02(X2,B2)
Store CPU Timer (p) STPT B209 S 02(B2) Subtract Normalized, Short Ic) SER 3B RR R1,R2 Store Halfword STH 40 RX R
1,02(X2,B2) Subtract Normalized, Short Ic) SE 7B RX R
1 ,D2IX2,B2) Store Multiple STM 90 RS R1.R3,D2(B2) Subtract Unnormalized, Long (c) SWR 2F RR R1,R2
Store Prefix (p) STPX B211 S 02(B2) Subtract Unnormalized, Long (c) SW 6F RX R1,02(X2,B2)
Store Then AND System STNSM AC SI 01 (B1),12 Subtract Unnormalized, Short (c) SUR 3F RR R1,R2 Mask (p) Subtract Unnormalized, Short Ic) SU 7F RX R1,02(X2,B2)
Store Then OR System Mask Ipl STOSM AD SI 01(B1),12 Subtract (c) SR 1B RR R1,R2
EXTENDED MNEMONIC INSTRUCTIONSt Subtract (c) S 5B RX R1,02(X2,B2)
Extended Code * Machine Instr. * Subtract Decimal (c) SP FB SS 01 (L 1,B1 ),02(L2,B2)
Use (RX or RR) Meaning (RX or RR) Subtract Halfword (c) SH 4B RX R1,02(X2,B2) Subtract Logical Ic) SLR 1F RR R1,R2 General B or BR Unconditional Branch BC or BCR 15, Subtract Logical (c) SL 5F RX R 1,021X2,B2) NOP or NOPR No Operation BC or BCR 0, Supervisor Call SVC OA RR I After BH or BHR Branch on A High BC or BCR 2, Test and Set (c) TS 93 S 02(B2) Compare BL orBLR Branch on A Low BCor SCR 4, Test Channel (c,p) TCH 9FOO S D2(B2)
Instructions SE orBER Branch on A Equal B BC or SCR 8, Test I/O (c,p) TIO 9000 S 02(B2) IA:B) BNH orBNHR Branch on A Not High BC or BCR 13, Test under Mask (c) TM 91 SI 01(B1),12 BNL or BNLR Branch on A Not LQw BC or BCR 11,
Translate TR DC SS 01(L,B1),02(B2)
BNE or BNER Branch on A Not Equal B BC or BeR 7, Translate and Test (c) TRT DO SS 01 (L,B1 ),02(B2)
After BO orBOR Branch on Overflow BC or BCR 1, Unpack UNPK F3 SS 01 (L 1,B1 ),02(L2,B2)
Arithmetic BP orBPR Branch on Plus BC or BCR 2, Write Direct (p) WRO 84 SI 01lB1),12 Instructions BM orBMR Branch on Minus BC or BCR 4, Zero and Add Decimal (c) ZAP F8 SS 01 IL 1,B1 ),02(L2,B2)
BNPorBNPR Branch on Not Plus BC or BCR 13, BNM orBNMR Branch on Not Minus BC or BCR 11, FloatinltPoint Instructions BNZorBNZR Branch on Not Zero BCor SCR 7, DP FOR· BZ or BZR Branch on Zero BC or BCR 8, NAME MNEMONIC CODe MAT OPERANDS After Test BO orBOR Branch if Ones BC or SCR 1, Add Normalized, Extended (c,x) AXR 36 RR R1,R2
under Mask BM orBMR Branch if Mixed BC or BCR 4, Add Normalized, Long (c) AOR 2A RR R1,R2
Instruction BZ or BZR Branch if Zeros BC or BCR 8, Add Normalized, Long Ic) AD 6A RX R1,02(X2,B2) BNO orBNOR Branch if Not Ones BC or BCR 14,
Add Normalized, Short (c) AER 3A RR R1,R2
Add Normalized, Short Ic) AE 7A RX R
1,02(X2,B2) tSource: GC33-401 0; for ·Second operand, not shown, is D2(X2,B2)
Add Unnormalized, Long (c) AWR 2E RR R1,R2 OSIVS,VM/370 and DOSIVS. for R
X format and R2 for R
R
format.
Add Unnormalized, Long (c) AW 6E RX R1,02IX2,B2) Add Unnormal'ized, Short Ic) AUR 3E RR R1,R2 SOME EDIT AND EDMK PATTERN CHARACTERS (in hex) Add Unnormalized, Short (c) AU 7E RX R1,D2(X2,B2)
20-digit selector 40-blank 5C-asterisk
c. Condition code is set. p. Privileged instruction.
21-start of significance 4B-period 6B-comma
n. New condition code is loaded. x. Extended precision floating-point.
22-field separator 5B-dollar sign C309-CR

CONDITION CODES 0 Condition Code Setting 0 1 2 3
Mask Bit Value 8 4 2 1
General Instructions Add, Add Halfword zero <zero >zero overflow
Add Logical zero, not zero, zero, not zero,
no carry no carry carry carry
AND zero not zero
Compare, Compare Halfword equal 1st op low 1st op high
Compare and Swap/Double equal not equal
Compare Logical equal 1st op low 1st op high
Exclusive OR zero not zero I nsert Characters under Mask all zero 1st bit one 1st bit zero
Load and Test zero <zero >zero
Load Complement zero <zero >zero overflow
Load Negative zero <zero
Load Positive zero >zero overflow
Move Long count equal count low count high overlap OR zero not zero Shift Left Double/Single zero <zero >zero overflow Shift Right Double/Single zero <zero >zero Store Clock set not set error not oper Subtract, Subtract Halfword zero <zero >zero overflow
Subtract Logical not zero, zero, not zero,
no carry carry carry
Test and Set zero one
Test under Mask zero mixed ones
Translate and Test zero incomplete complete
Decimal Instructions
Add Decimal zero <zero >zero overflow
Compare Decimal equal 1st op low 1st op high
Edit, Edit and Mark zero <zero >zero Shift and Round Decimal zero <zero >zero overflow
Subtract Decimal zero <zero >zero overflow Zero and Add zero <zero >zero overflow
Floating-Point Instructions
Add Normalized zero <zero >zero
Add Unnormalized zero <zero >zero
Compare equal 1st op low 1st op high
Load and Test zero <zero >zero
Load Complement zero <zero >zero
Load Negative zero <zero
Load Positive zero >zero
Subtract Normalized zero <zero >zero
Subtract Unnormalized zero <zero >zero Input/Output Instructions
Clear I/O no oper in CSW stored chan busy not oper
progress
Halt Device interruption CSW stored channel not oper
pending working
Halt I/O interruption CSW stored burst op not oper
pending stopped Start I/O, SIOF successful CSW stored busy not oper Store Channel I D ID stored CSW stored busy not oper
Test Channel available interruption burst mode not oper
pending
Test I/O available CSW stored busy not oper
System Control Instructions
Load Real Address translation ST entry PT entry length
available invalid invalid violation
Reset Reference Bit R=O,C=O R=O, C=1 R=1, C=O R=1,C=1 Set Clock set secure not oper
Signal Processor accepted stat stored busy not oper CNOP ALIGNMENT DOUBLEWORD WORD I WORD HALFWORD I HALFWORD I HALFWORD I HALFWORD
BYTE BYTE I BYTE I BYTE I BYTE • BYTE I BYTE • BYTE 0,8 2,8 4,8 6,8 ASSEMBLER INSTRUCTIONSt ® Function Mnemonic Meaning
Data definition DC Define constant DS Define stllrage CCW Define channel command word
Program START Start assembly
sectioning CSECT Identify control section
and linking DSECT Identify dummy section
DXD* Define external dummy section
CXD* Cumulative length of external dummy section COM Identify blank common control section
ENTRY Identify entry-point symbol
EXTRN Identify external symbol
WXTRN Identify weak external symbol
Base register USING Use base address register
assignment DROP Drop base address register
Control of listings TITLE Identify assembly output
EJECT Start new page SPACE Space listing PRINT Print optional data
Program Control ICTL Input format control ISEQ Input sequence checking
PUNCH Punch a card REPRO Reproduce following card ORG Set location counter
EQU Equate symbol OPSYN* Equate operation code PUSH * Save current PRINT or USING status POP * Restore PRINT or USING status LTORG Begin literal pool CNOP Conditional no operation COpy Copy predefined source coding
END End assembly
Macro definition MACRO Macro definition header MNOTE Request for error message MEXIT Macro definition exit
MEND Macro definition trailer
Conditional ACTR Conditional assembly loop counter
assembly AGO Unconditional branch AIF Conditional branch ANOP Assembly no operation
GBLA Define global SETA symbol
GBLB Define global SETB symbol
GBLC Define global SETC symbol
LCLA Define local SETA symbol
LCLB Define local SETB symbol
LCLC Define local SETC symbol SETA Set arithmetic variable symbol SETB Set binary variable symbol SETC Set character variable symbol
SUMMARY OF CONSTANTSt IMPLIED LENGTH, TYPE BYTES ALIGNMENT FORMAT C
- byte characters
X -byte hexadecimal digits
B -byte binary digits
F 4 word fixed-point binary
H
2 halfword fixed-point binary
E 4 word short floatin!}-point D
8 doubleword long floating-point
L 16 doubleword extended floating-point
P -byte packed decimal Z - byte zoned decimal
A 4 word value of address
Y 2 halfword value of address S 2 halfword address in baslHlisplacement form
V 4 word externally defined address value
Q* 4 word symbol naming a DXD or DSECT tSource: GC33-4010; for OS/VS, VM/370, and DOS/VS. ·OS/VS and VM/370 only. TRUNCA- TIDNI PADDING right
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