A specific line base is assigned as the first line
base within the continuous span of addresses. Then
a line set of eight line adapters is added for this line
base. As many lines as desired (up to eight lineE for start/ stop, or four lines for synchronous opera­
tion) are attached to this line set. Addresses are
assigned to all eight lines even if lines are not attached. ¥lhen the first line base is filled--or has as many lines
attached as desired--the addresses are assigned to the
second line base in the same manner. Similarly, ad­
dresses are assigned to the third line base if it is
attached to the 2703.
If two 2703's are placed on the channel, the
second 2703 may be placed with its lowest address
in the next increment of 16 not assigned to the first
2703. Address assignment has no bearing on the
priority of any particular line. This is a function of
the type of line base only.
Address-Assignment Considerations
Numerous things should be considered when deter­
mining the 2703 address assignments. However,
all these various items can be associated with the
following list of major considerations involving
address assignment:
1. A multiplexer channel can accommodate a
maximum of 256 individual addresses. NOTE: Each address is associated with an individual sub channel
within the multiplexer channel. ThE: c:apabilitics of a specific channel are
dictated by the IBM System/360 processor
model employed and the available core storage.
Refer to "Maximum Lines Available by
Processor Model. " 2. The specific address range available for
assignment is 0 to 255.
3. Any one 2703 is limited to a maximum of 176
individual addresses (or lines).
4. The low-address boundary for address assign­
ment should be either 0 or a 16-unit increment
thereof (for examp!e--1&, 32, or 48). NOTE: A boundary of 48 should be used if convenient. This start­ ing number reserves sufficient positions to allow the channel ;,tt:ichmcnt of other devices with standard assigned addresses (for example, the standard assigned address for the 1050 Docu­
mentary Console is 31 or'1F'*). This also simplifies installa­
tion, since the low-boundary address of 48 is prewired before
5. The high-address boundary must be an even
increment of either 8 (for startl stop) or 4
(for synchronous) from the low-address
boundary within the 2703.
6. The 10\\lest address within the 2703 is always
assigned as the wrap address. The wrap i< , , is Hexadecimal representation.
address is the address of the line used to read
data back to the channel from any line issued
the Wrap command. The wrap address and its
associated line can be used for normal trans­
mission at all times, except when the 2703
is being checked with a Wrap command. Refer
to "Automatic Wrap-around" under "Program­ ming Considerations. " Maximum Lines Available by Processor Model
Each half-duplex communications line requires a
separate subchannel within the multiplexer channel.
The addresses for these lines are assigned sequen­
tially on the 2703, normally starting at address 16.
(See item 4 under "Address-Assignment Considera­
tions. ") A second 2703 can be attached to the
same channel. The low -address bounda.ry of the
second 2703 is the first available address in the next
increment of 16 above the first 2703. Different
numbers of subchannels are available on the IBM
System/360 Models 30, 40, 50, 65, and 75. The
maximums are given in the following as a function
of the processor and the minimum core-storage
size. In the case of the mM 2780 Multiplexer
Channel, the number of subchannels is not dependent
on the core storage available.
Processor Number of Minimum Core-StoragE
Model Sub channels
Model C 30 Model D 30 Model ElF 30 Model D 40 Model E 40 Model F 40 Model G/H 40 Model F 50 Model G 50 Model HII 50 Processor Model
with 2870
Model 65
Model 75
Number of
Size (Bytes)
32K-64K and
Feature #5250* 16K
256K-512K and
Feature #5250* *Additional Multiplexer SubchalUlels special feature
Channel-Attachment Restrictions
The following restrictions pertain to the attachment
of any 2703 to the multiplexer channel.
1. The 2703 should have the first control-unit
position on the channel; in other words, it
should be the first to receive the channel­
scanning signals. When hvo 2703's appear on
the same channel, they will have sequential priority.
2. No shared subchannels will be allowed on the
multiplexer channel when more than 128 sub­
channels are required. In any case, if devices
using a shared subchannel are physically
attached to the channel, they must not be operat­
ed while the 270;) is in operatlOn.
3. The maximum line speed for any lines attached
to the 2703 is:
Start/ stop type lines--600 bps
Synchronous (BSC) type lines--2400 bps
4. The maximum number of lines attached to any
one 2703 is determined by the type of lines and
line mix. Figure 8 provides a complete listing
of maximum lines by the various possible line­
The 2703 connects to and operates with the multi­
plexer channel via the I/O interface. This interface
consists of byte buses (In :;l1".d Out) and tag lines that
indicate the type of information on the byte buses
(e. g., command, address, data, and status),
channel-interlock controls, and interface-scanning
signals. The scanning Signals and interlocks estab­
lish priority among different 2703' s or other control
units attached to the multiplexer channel. When the 2703 requires data transfer on any of its communi­
cations lines (line 14, for example), the scanning
signal is intercepted by the 2703 and an interlock lead
is raised, indicating the interception of the scanning
signal to the multiplexer channel. The 2703 places
the address of the line requesting service on the
Input bus. When the 2703 receives acknowledgment
from the channel that the appropriate control word
lias been from storage, data transfer
between the 2703 and the channel begins. When transfer of a data byte (or bytes) is complete, the
interlock is dropped and the channel resumes scan­ ning the interface. Up to four data byieE can be
transferred serially by byte in one data-transfer
Selection of the next device (2703, card reader,
etc. ) is on a priority basis. However, the same 2703 is again selected if any line attached to this
unit requires service. and no higher-priority
machine on the channel interface is selected.
Usually the 2703 is attached to the multiplexer in
the position of highest priority.
The multiplexer channel initiates an operation to
a 2703 during the CPU execution of a Start I/O instruction. The specific 2703 operation desired is
defined in the channel-command word (CCW). Data
transfer in either direction across the I/O interface
is initiated by the I/O device after it is com manded . to start by the program.
1/ a Instructions
The System/360 operates with the 2703 through the follOWing I/O instructions: Start I/O, Halt I/O, and Test I/O. Start I/O A start I/O instruction executed by the CPU causes
initial command selection and the transfer of a
command byte to the 2703. Command chaining
within the multiplexer channel also causes selection
and transfer of a command to the 2703. However,
the 2703 will not signal Control Unit Busy status in
response to a command cycle resulting from comman(
chaining. This interlock is effected by presenting
unit status to the multiplexer channel only if the 2703 is free to accept a possible chained command.
During initial selection, the 2703 loads the line
address and the command byte into registers. The 2703 can make the following status responses to Start I/O: 1. If the command is acceptable to the 2703, an
all-zero status byte is sent to the channel.
2. If the command is not acceptable to the 2703, Unit Check is returned to the channel and the
reason for responding with Unit Check
(Command Reject or Bus-Out Check) is set in
the sense byte stored in MCW-2. 3. If the 2703 is busy, it signals Control-Unit
Busy to the multiplexer channel. Control­
Unit Busy is defined for the 2703 as the busy,
status -modifie r, and control-unit-end bits
being ON in the status byte transferred to the
channel. NOTE: This condition occurs only in cases where the channel
traffic is exceptionally high.
Halt I/O Once the 2703 has responded to initial command
selection, the channel can signal Halt I/O. When the 2703 detects a Halt I/O, it loads the line address into
a register, the same as for Start I/O. The addresse
l MCW is commanded to halt. When the current com- I
Previous Page Next Page