LOAD PSW
The LOAD PSW instruction is executed for a
virtual machine if the virtual-machine assist is
activated, unless (1) a virtual-machine interruption
may follow. (2) the second operand or some
pertinent VM/370 control field cannot be accessed,
(3) the PER mask is one in the real PSW or in the
old or the new virtual PSW, or (4) execution would
change the control mode, the DAT bit, or the
wait-state bit of the virtual PSW. The load- PSW function of the virtual-machine
assist is invoked each time a CPU attempts to
execute a LOAD PSW instruction when the
problem-state bit of the real PSW is one.
Execution of this function consists in performing
the following steps:
1. If bits 0-1 of control register 6 are not 10 binary, execution of the load-PSW function
ends, a program interruption takes place for a
privileged-operation exception, and execution
of the LOAD PSW instruction is suppressed
(1.A).
2. The second halfword of the LOAD PSW instruction is fetched. If an access condition is
encountered, execution of this function ends,
and a program interruption takes place for the
access exception encountered (l.B).
3. If bits 29-31 of the second-operand address are
not zeros or if the PER mask in the real PSW is
one, execution ends with a program
interruption for a privileged-operation
exception (2.A).
4. A doubleword is fetched with the logical
address of the second operand and the PSW key. If an access condition is encountered,
execution of this function ends with a program
interruption for the access condition found
(2.B.1).
5. Execution of the load-PSW function ends if
either of the following conditions is found
(2.B.2):
a. The new virtual PSW (second operand) has
the wait-state bit set to one.
b. The new virtual PSW has a one in bit
position 12 (EC mode) and bits 0-4, 16-17,
and 24-39 are not all zeros (PER mask is
one or a format error exists).
If execution ends, control passes to the load-PSW function of the expanded virtual­
machine assist if that facility is installed.
Otherwise, execution ends with a program
interruption for a privileged-operation
exception.
12 Virtual-Machine Assist and Shado\v-Table-Bypass Assist
6. The word MICVPSW, containing the virtual PSW address, is fetched with a key of zerO.
Execution ends if an addressing condition is
encountered (2.C.1).
7. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution ends if an addressing
condition is encountered (2.C.2).
8. Execution ends if the virtual PSW has ones in
bit positions 1 and 12 (PER mask is one in the
EC mode). If execution ends, control passes to
the load-PSW function of the expanded
virtual-machine assist if that facility is installed. Otherwise, execution ends with a program
interruption for a privileged-operation
exception (2.C.3.A).
9. Execution of the load-PSW function ends if any
of the following conditions holds (2.C.3.B):
a. The control mode of the virtual PSW is
being changed from the BC to the EC
mode, or from the EC mode to the BC
mode.
b. The DA T -mode bit of an EC-mode virtual PSW is being changed.
c. A virtual interruption is pending, and any
channel mask, input/output mask, or
external mask is being changed from zero
to one (bits 0-7 in the BC mode and bits
6-7 in the EC mode). A virtual
interruption is pending when bit 0 of MICVPSW is one.
Note that, because all these conditions
require the value fetched in step 4, this step
necessarily has a lower priority than step 4
despite the priority rules based on priority
indicators.
If execution ends, control passes to the load-PSW function of the expanded virtual­
machine assist if that facility is installed.
Otherwise, execution ends with a program
interruption for a privileged-operation
exception. 10. The key, the condition code, the program mask,
and instruction-address-field values of the new
virtual-machine PSW replace the corresponding
fields in the real PSW. Bit 15 of the virtual­
machine PSW is placed in bit position 1 of
control register 6. The new virtual-machine PSW is stored, with a key of zero, in VMPSW (3).
Figure 8 summarizes the fields used.

Field Control Address Offset No. of
Name Block Type (Hex) Bytes Contents i I i - I I __ I ____ I __ _ IVMPSW iVMBLOK--tReal 1- I Oper and 2\ - I Log i ca 1 I ' . - . .. - .. q + 4 IAadress ot ' -0- I - i-tv i rtua 1 PSW -b-fts-O:'-lst - I 8 INew virtual PSW I ! . I I I I I I Figure 8. Fields Used in LOAD PSW LOAD REAL ADDRESS The LOAD REAL ADDRESS instruction is
executed for a virtual machine if the virtual­
machine assist is activated for System/370
instructions, unless (1) a virtual-machine exception
is recognized, or (2) some pertinent VM/370 . control field cannot be fetched.
If the shadow-tabIe-bypass assist is not installed,
the load-real-address function of the virtuaI­
machine assist is invoked each time a CPU attempts
to execute a LOAD REAL ADDRESS instruction
when the problem-state bit of the real PSW is one.
If the shadow-table-bypass assist is installed, the
load-real-address function of the virtual-machine
assist may be invoked only from the load-real­
address function of the shadow-table-bypass assist.
Execution of this function consists in performing
the following steps:
1. If bits 0-3 of control register 6 are not 10XO binary, execution of the load-real-address
function ends, and a program interruption takes
place for a privileged-operation exception
( l.A.1).
2. The doubleword containing the fields
MICRSEG and NHCCREG is fetched with a
key of zero. MICRSEG contains the address of
the real segment table, and MICCREG contains
the address of the extended control block
(ECBLOK). Execution ends if an addressing
condition is encountered (l.A. 2).
3. The first doubleword (EXTCRO and EXTCR1,
virtual control registers 0 and 1) of the
extended-control block (ECBLOK) is fetched
with a key of zero. Execution ends if an
addressing condition is encountered (l.A.3).
4. Execution of this function ends with a program
interruption for a privileged-operation
exception if bits 8-12 of virtual control register
o have an invalid format (l.A.4).
5. The second halfword of the LOAD REAL
ADDRESS instruction is fetched. If an access
condition is encountered, execution of this
function ends, and a program interruption takes
place for the access exception encountered
( l.B).
6. The segment index, the page index, and the
byte index of the second-oper.and address are
found. They are selected from effective­
address positions dependent on bits 8-12 of
virtual control register O. For a virtual segment
of 64K bytes, execution ends if the segment­
table-length value in bit positions 0-7 of virtual
control register 1 is less than the value obtained
by appending four zeros to the left of bits 8-11
of the second-operand address. In that case,
condition code 3 is set, and the virtual address the segment-table entry that would have
been referred to had no length violation existed
is placed in the general register specified by the
Rl field of the instruction (2).
7. The virtual address of the virtual segment-table
entry is computed. The real segment index and
the real page index of the virtual address of the
virtual segment-table entry are found. The real
page size is 4K bytes or 2K bytes as bit 30 of
MICRSEG is zero or one; the real segment size
is 64K bytes or 1M byte as bit 31 of
MICRSEG is zero or one. For a 64K-byte
segment, execution ends with a program
interruption for a privileged-operation
exception if the segment-table-length value in
bit positions 0-7 of MICRSEG is less than the
value obtained by appending four zeros to the
left of bits 8-11 of the virtual segment-table­
entry address (3).
8. The address of the real segment-table entry,
SEGPAGE, for translating the virtual
segment-table-entry address is computed. This
address is used with a key of zero to fetch the
corresponding real segment-table entry.
Execution ends if an addressing condition is
encountered (4). q Execution ends with a program interruption for
a privileged-operation exception if the fetched
entry is invalid or has an invalid format or if
the leftmost four bits of the real page index of
the virtual segment-table entry address are
greater in value than bits 0-3 of the real
segment-table entry fetched (5).
Virtual-Machine Assist 13
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