I I I \ I I ! 10 of the assist control word are not both ones
(1.A.3).
4.
If an access exception is encountered in
fetching the second or third halfwords of the TPROiiTIStruction, executiull-ot-ti1is-iurrctton­ ends, and a program interruption takes place
for the access exception (l.B).
5. The TPROT instruction is executed just as if
the real problem-state bit were zero. If any
exception is recognized, a program interruption
takes place and indicates that exception in the
normal manner. Otherwise, the condition code
is set, and execution of the TPROT instruction
is completed (2).
Figure 29 summarizes the fields used.
Page-Fault Reflection
The page-fauh-reflection function of the shadow­
table-bypass assist performs a program interruption
in the virtual machine for a page-translation
exception if the real PSW and the old and new
virtual PSWs meet specified conditions.
The page-fault-reflection function is invoked
each time the System/370 architecture calls for a
program interruption for a page-translation
exception when the problem-state bit of the real PSW is one. The execution of this function
consists in performing the following steps:
1. Execution ends and a program interruption for
a page-translation exception takes_ place if the
VM-assist hit (bit 0 of control register 6) is not
one (1).
2. On some models, the segment index and the
page index of the untranslatable address are
placed in the word at real location 90 hex. If
the virtual-machine assist is installed and the
shadow-table-validation bit (bit 5 of control
register 6) is one, this function is completed by
transferring control to the shadow-table­
validation function of the virtual-machine
assist. If the virtual-machine assist is not I Field Control Address Offset No. of
Name Block Type (Hex) Bytes Contents installed, no test is performed, and control
remains in the page-fault-reflection function
(2). Steps 3 through 8 describe conditions that cause(iprogram ill tel I up lion irr-the-reat
u machine for the original page-translation
condition:
3. The assist control word, MICACF, is fetched
with a key of zero. Execution is completed if
an addressing condition is encountered (3.A.l).
4. Execution is completed if bits 8 and 11 of the
assist control word are not both ones (3.A.2).
5. MICVPSW, which contains the address of the
virtual PSW, is fetched with a key of zero.
Execution is completed if an addressing
condition is encountered (3.B.l).
6. VMPSW, the virtual PSW, is fetched with a key
of zero. Execution is completed if an
addressing condition is encountered (3.B.2).
7. Execution is completed if in the virtual PSW bit
1 is one or bit 12 is zero (3.B.3).
8. Execution is completed if real PER is on (3.C).
Real address 0 is translated through the
segment tables addressed by the first word in
the virtual-machine parameter list. Steps 9
through 16 describe conditions that cause a
program interruption in the real machine for
the original page-translation condition.
9. An addressing exception is encountered in
fetching the word MICRSEG with a key of
zero. MICRSEG contains the address of the
real segment table (4). 10. Bits 30 and 31 of the word containing the
address of the real segment table are not both
zeros (5).
11. The first segment-table entry, SEGPAGE, in
the real segment table cannot be fetched with a
key of zero because of an addressing exception
(6).
12. SEGPAGE is invalid.
13. SEGPAGE has a format error (8). I MICACF MICBLOK Real 14 4 Assist control word
Virtual
- - 4 [segment-table entry I I Virtuall I I - Page Real I - I 2 Page-table entry
table ,Operand 2 -Logical 1 1 Byte tested i Figure 29. Fields Used in TEST PROTECTION
Shadow-Table-Bypass Assist 39

14. The first page-table entry, PAGCORE, in the
table addressed by the segment-table entry
cannot be fetched with a key of zero because
of an addressing exception (9).
15. PAGCORE is invalid (10). 16. P AGCORE has a format error (11).
17. The new virtual PSW is fetched with a key of
zero from offset 68 hex in virtual page O. Execution of this function ends if an addressing
condition is encountered (12).
18. The new virtual PSW is tested for BC mode,
DA T on, PER on, wait-state bit one, and
format errors. If a virtual interruption is
pending, tests are made to determine whether
the input/output mask or the external mask is
being changed from zero to one. If any of
these conditions is found, a program
interruption takes place in the real machine for
the original page-translation condition (13).
A program interruption takes place in the
virtual machine for the original page-translation
condition. This interruption consists in
performing steps 19 through 27.
19. The old PSW, consisting of bits 0-15 from the
current virtual PSW and bits 16-63 from the
real PSW, is stored at virtual-machine location
28 hex with a key of zero (14.A). 20. The program-interruption identification word is
stored with a key of zero at virtual-machine 40 Virtual-Machine Assist and Shadow-Table-Bypass Assist
location 8C hex. This word consists of zeros in
bits 0-12 and 15, the instruction-length code in
bits 13-14, and the page-translation-exception
code, 0011 hex, in bits 16-31 (14.B).
21. A word is stored at location 90 hex of the
virtual machine with a key of zero. This word
contains the segment and page indexes of the
address for which the original page-translation
exception was detected (14. C).
22. Bits 0-15 of the new virtual PSW replace the
virtual PSW, VMPSW, in storage accessed with
a key of zero (14.D).
23. Bits 8-12 of the real control register 0 are set
to 10000 binary (14.E.l.A).
24. Real control register 1 is loaded with the real
segment-table pointer (MICRSEG) (14.E.l.B).
25. Real control registers 0 and 1 are stored in a
double word at a fixed location in the real PSA (RUNCRO and RUNCRl) with a key of zero
(14.E.2).
26. Bits 16-63 of the new virtual PSW are placed
in the corresponding positions of the real PSW (14.F).
27. Bit 15 of the new virtual PSW is placed in bit
position 1 of control register 6 (14.G).
28. Execution of the current function is completed,
and virtual instruction execution is nullified
(15).
Figure 30 summarizes the fields used.