Introduction
This manual was written to provide an understanding of the microprogramming language for
the people involved with creating or interpreting microprograms on the IBM System 360-Model 30.
]VIicroprogramming provides the control for most of the functions performed in the IBM System
360-Model 30. These functions consist of memory control, Arithmetic and Logic Unit Controls
(ALU), hardware register input and output controls, machine status controls, Read Only Storage
(ROS), sequencing controls and some I/O controls.
The microprogramming instructions are explained individually to simplify the complexity of
the microprogramming language. Each instruction has a description of the control field bit struc-
ture, branching conditions, hardware registers and latches, and buss and tag lines involved. Charts
are also provided for timings, microword formats, data-flow and local storage layout to clarify the
microprogramming functions.
Model 30 Machine Control Specifications
The Read Only Storage (ROS) must provide control for most of the functions performed in the
Model 30. These functions, to repeat, consist of memory control, ALU (Arithmetic and Logic Unit)
controls, hardware register input and output controls, machine status controls, ROS sequencing
control and some I/O control.
The Data Flow Chart for the Model 30 is shown in the Appendix. The breakdown of the ROS
output, as punched in a bit card, can also be found in the Appendix. A GEOG address is the loca-
tion of the ROS word on the microprogramming flow diagram. The HEX address is the location of
the word in the ROS. The output is described in columns 11 through 72 (62 bits) of the CCROS
Document Card.
The ROS output is divided into subfields called control fields. Some control fields may be de-
coded and used directly from the Sense Amplifier Latches (SAL). Some control fields require a con-
trol register to hold the ROS output information until it is used.
Control Field Description
CN-6 Bits
PN-I Bit
PA-I Bit
CH-4 Bits
CL-4 Bits
CM-3 Bits
.#CU-2 Bits
#CA-4 Bits
AA-I Bit
CB-2 Bits
#CK-4 Btis
AK-I Bit
PK-I Bit
PS-I Bit
Next ROS address
Odd parity on CN
Odd parity on address of ROS word
ROS address branching
ROS address branching
Address register/read write select
Main storage or local storage data destination
Input source for A buss and A register
Alternate CA decoder bit
Input source for B buss and B register
Constant generator
Alternate CK decoder bit
Parity for CK field
Odd parity for SAL's
IBM Confidential
1\

*CD--4 Bits
*CF-3 Bits
*CG-2 Bits
*CV-2 Bits
*CC-3 Bits
#
*CS-4 Bits
*AS-I Bit
*PC-I Bit
Destination from Z buss
Controls the Hi/Lo, crossed/straight functions of the A register entry into
theALU
Controls the Hi/Lo functions of the B regisi;er entry into the AL U
True/complement and Binary/decimal controls
Carry control and logic control
Status control
Alternate CS decoder bit
Odd parity on control registers
#-Fields with alternate decoders
*-Fields with control register
Control Field (Detailed Explanations)
CN Field
PN Field
PA Field
CH and CL Fields
2
IBM Confidential
The high order 6 bits of the ROS address register X are loaded from the
CN field.
Provides odd parity on CN for generating parity on X when the other two
bits of X are known.
Provides a check on the word read from ROS.
It
is odd parity on the 12 bit
address WX.
These fields handle the branching of the ROS address. The CH field con-
trols the X register 6 bit in the ROS address register, and the CL field con-
trols the X register 7 bit. All conditions must be set before the cycle in
which the branch is interrogated.
CH
=
0000 or 000 I
In this condition the constants are used for forced branching. CH
=
0000
forces the X register 6 bit off (0), and CH
=
0001 forces the X register 6
bit on (1). (See example lA, page 17.)
CH = 0010 (RO)
This is a branch on a latch in the R register.
If
the R register 0 bit is a 1,
the X register 6 bit is forced on (1), satisfying the branch condition.
CH
=
0011 (V67
=
0) (GMWM-If 1401 feature)
This is a conditional branch.
If
the V register 6 and 7 bits are 0, the X reg-
ister 6 bit is forced on (1), satisfying the branch condition. The GMWM,
if a 1401 feature, is a conditional branch. (See example 1B, page 17.)
CH
~
0100 (STI)
This is a conditional branch. If the status-in-line (Multiplex Channel) for
the interface is up, the X register 6 bit is forced on (1) satisfying the
branch condition. (See example IB, page 17.)
CH = 0101 (OPI)
This is a conditional branch.
If
the operational-in-line (Multiplex Channel)
for the interface is up, the X register 6 bit is forced on (1), satisfying the
branch condition. (See example IB, page 17.)
CH = 0110 (AC)
This is a conditional branch. If an adder carry resulted in the previous
cycle, the X register 6 bit if forced on (1), satisfying the branch condition.
(See example 1B, page 17.)
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