REA 0 W R I T E REA 0 COMPUTE
W R I T E
TI T2 T3 T4 Tl T2 T3 T4 Tl T2 T3 T4 T1 T2 T3
T4 TI T2
T3
T4
I---
r-----
WR I TE CALL --
I---
r---
SET MN AND READ CALL
----
MN GOOD __
-§}
I.J
STROBE SET __
850-H I-
1100
I I
R GOOD -_
L
U
I---
r---
r---
~
SET AB __
--
ADD ANSWER GOOD
600-
H I
r
r
r
ADD PARITY GOOD
793-
W-
I I
,--
I
~
r---
I---
SET DESTlNATlON __
r--
I---
~
r--
SET
ROSAR---
-J~~
ROSAR GOOD __
U
W U U
r--
I---
ROSAR GO_
SALS GOOD __
600-
r-L
U--
780
L
U
L
U
L
U
L
U
.-
I---
~
I--- I---
SET CONTROL REG __
-
--l}-
CONTROL REG GOOD--
100
U
W
U
U
ALLOW WR I TE --
CPU READ __
--
600-H
780-
H l
CPU WRI TE --
780 -
H
600-I-t
r
,
Figure A-3 Timing Chart

~
~
......
txl
as::
(")
0
::
";:t,
....
'"
~
~
OX
IX
2X
3X
4X
5X
CPU
6X
LOCAL
7X
STORAGE
8X
9X
AX
BX
CX
OX
EX
FX
OX
IX
2X
3X
4X
5X
UCW
6X
LOCAL
7X
STORAGE
8X
9X
AX
BX
CX
OX
EX
FX
2030 LOCAL STORAGE MAP
o
23456 789ABCDEF
G.P. REG.
o
~~A:
I
xl
X+ 11 X+2 FLOATI NG POI NT
R~G
0
1
/
2 1050
'
Use lFLOATING POINT REG 2
3
W'/!I~ CPUI~
4
~*~E
FLOATING
POINT REG
4
5
lEOCS
0 L S V
U G
J
I
6 VII/I///f/, FLOATING POINT REG 6
7
FLOAT I NG PT. MULTIPLY
8
0 1 2
3
4
5
6
7
9 R 9
10 11 12 13 14 15
A 16
17 18 19 20 21
22
23
B
24 2S 26 27 28 29 130 31
C
0
E
CPU WORKING STORAGE
F
UNIT
CONTROL WORD
0
UNIT CONTROL WORD 16
l
17
2
18
3
19
4
20
5
21
6
22
7 23
8
24
9 25
10
26
11
27
12
28
13 29
14 30
15
31
O-MP
I-MP
2-MP
3-MP
4-PS
5-SE
6-SE
7-SE
8-MP
9-10
TO"}
Il-
12-
13-
14-
15-
*1
K ADDRESSABLE
LS BYTES
(1.0,CNO, KO, 1 ,K 1 ,K2, K3)
PARI TY=KP=ODD
K-ADDRESSABLE BYTE UTILIZATION
X lB UN ADDR
X T STORE
X R STORE
X IB UN STATUS
W BIT
&
ILC
L 1 UNIT ADDR
L 1 NXT CCW HI
L 1 NXT CCW LO
X UA TEMP STG
50 USAGE
CPU
WORKING
STORAGE
16-INST CNTR UNAVAIL
17-INST CNTR HI
18-INST CNTR LO
19-HSMX UNIT ADDR K**
20-SEL CHAN R STORE
21-SEL 2 UNIT ADDR }
22-SEL 2 NXT CCW HI **
23-SEL 2 NXT CCW LO
24-SYSTEM MASK
25-STOR PROT
&
MONITOR
26-HSMX UNIT ADDR.
27-COND REG
&
PGM MSK
28-
29-SEL CHAN S STORE
30-SEL CHAN U STORE
31-SEL CHAN V STORE
**TENATIVELY RESERVED FOR
HIGH SPEED MULTIPLEX
CHANNEL (HSMX) (HSMX
MUTUALLY EXCLUSIVE WITH
2ND SEL CHNL)
CPU LS LOCATIONS 34,35,44,45,55,56,66,67 WILL BE USED
BY THE HIGH SPEED MULTIPLEX CHANNEL
FOR THE STORAGE OF NEXT CCW ADDRESSES
PER SUBCHANNEL
Figure A-4 2030 Local Storage Map
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