The Exclusive OR function
(v-)
requires no coincidence of bits to obtain an output.
13 CS FIELD-STATUS
A. CS
=
0001, 0010, 0011, and 1001
- R
+
D-C
LZ-S5
Must be tested in the same cycle as the arithmetic statement that generates the condition.
B. CS
=
1110
-
K
=
lOOO'PO
K
=
1001
PI
o
+ KH--S
K-FB
SIL.
16K SLL
32K
SR
64K S
11..
IJ -MN MPX
8K
STORAGE
8K
STORAGE
16K
STORAGE
32K
STORAGE
g
B
g
g
Bump #1
Bump #2
Bump
#3
Bump
#4
Bump
#5
Bump #6
Bump
#7
Bump
#8
IBM Confident;t"
29

SK
IJ
~
MN MPX does not force any M register bits on.
It
also addresses Bump #1.
IJ
~
MN LS forces the M register 3 bit on, and addresses Bump #2.
16K
IJ
~
MN MPX does not force any M register bits on.
It
also addresses Bump
#1.
XL latch on-IJ
~
MN MPX forces the M register 3 bit on, and addresses Bump #2.
SH latch on-IJ
~
MN MPX forces the M register 2 bit on, and addresses Bump #3.
IJ
~
MN LS forces the M register 2 and 3 bits on, and addresses Bump #4.
32 or 64 K
IJ
~
MN MPX does not force any M register bits on.
It
also addresses Bump #1.
XL latch on-IJ
~
MN MPX forces the M register 3 bit on, and addresses Bump #2.
XH latch on-IJ
~
MN MPX forces the M register 2 bit on, and addresses Bump #3.
XL, XH latches on-IJ
~
MN MPX forces the M register 2 and 3 bits on, and addresses
Bump #4.
XXH latch on-IJ
~
MN MPX forces the M register 1 bit on, and addresses Bump #5.
XL, XXH latches on-IJ
~
MN MPX forces the M register 1 and 3 bits on, and addresses
Bump #6.
XH, XXH latches on-IJ • MN MPX forces the M register 7 and 2 bits on, and addresses
Bump #7. .
IJ. MN LS forces the M register 1, 2 and 3 bits on, and addresses Bump #8.
30
IBM Confidential