Bits of
Word 4 0-7 8-31
Bits of
Word 5
MICVTMR
These bits are not used.
Real address of virtual-intervaHimer word (bits MICACF 0-7 Each of the] 1 functions of the expanded
virtual-machine assist can be activated only
when a specific bit in this group is one.
8 The functions of the shadow-table-bypass assist
can be activated only when this bit is one.
9-15 Each of the eight functions of the shadow­
table-bypass assist can be activated only when
a specific bit in this group is one.
16- 31 These bits are not used.
Programming Note Placing nonzero values in unused positions of
control register 6 or the parameter list is
inadvisable because these positions may be used
later and could cause incompatible execution.
Interaction of VM/370 Assists
Where the same virtual-machine instruction may be
executed by more than one VM/370 assist, a fixed
order exists among the assists in which similar
functions are invoked. This order is (1) shadow­
table-bypass assist, (2) virtual-machine assist, and
(3) expanded virtual-machine assist. Thus, for a STORE THEN AND SYSTEM MASK instruction
for a virtual machine, the STNSM function of the
shadow-table-bypass assist is invoked. That
function may (1) complete execution of the
instruction, (2) exit via a program interruption, or
(3) exit by invoking the STNSM function of the
virtual-machine assist. The latter function may in
turn (1) complete execution of the instruction, (2)
exit via a program interruption, or (3) exit by
invoking the STNSM function of the expanded
virtual-machine assist.
Similarly, a page-translation condition may
invoke the shadow-table-validation function of the
virtual-machine assist or the page-fault-reflection
function of the shadow-table-bypass assist if one of
those assists is installed. If both assists are
installed, the page-fault-reflection function of the
shadow-table-bypass assist is invoked first for a pagE'-translation condition. This function may result in (1) a virtual-machine program
inlerruption, (2) a real-machine program
interruption, or (3) invocation of the shadow­
table-validation function of the virtual-machine
assist.
Interaction of VM/370 Assists with Other Facilities
Control Mode
The virtual-machine assist and the shadow-table­
bypass assist are defined to operate only on a CPU
which is in the EC mode.
Program-Event Recording
When any assist for VM/370 completely executes a
virtual-machine instruction, a program interruption
takes place in the real machine for PER events if
the real PER mask is one and in accordance with
the settings of the PER controls in real control
registers 9, 10, and 11. Storage-alteration events
are indicated only for changes to virtual-machine
storage. Changes in VM/370 control blocks in real
storage are not indicated. However, a PER mask
of one in the real or virtual PSWs may cause a
virtual-machine-instruction assist function to exit
by taking a program interruption before completely
executing the instruction, The-- specific rules governing the effect of PER
mask values on the execution of VM/370 assist
functions are:
1. The PER indication is unpredictable for the
instructions of control-program assist.
2. A real PER mask value of one prevents a
virtual-machine external interruption for a
virtual interval-timer request.
3. A real PER mask value of one causes those
expanded -virtual-machine-assist functions
which can only partially execute a virtual­
machine instruction to exit with a program
interruption for a privileged-operation
exception.
4. Load-PSW and supervisor-call functions of all
assists exit by a program interruption for a
privileged-operation exception or by a
supervisor-call interruption if the PER mask is tJle real pS.W, in the current virtual PSW, or in the new virtual PSW. 5. Set-system-mask, store-then-AND-system­
mask, and store-then-OR-system mask
functions whose definition allows complete
execution under certain conditions exit with a
program interruption for a privileged-operation
exception if an attempt is made to change the PER mask in the virtual PSW. 6. Shadow-table validation and page-fault
reflection are inactive when the real PER mask
is one.
Assists for VM/3 70 5
Dynamic Address Translation
In general, references to VM/370 control blocks in
storage use real addresses and are thus not subject
to translation by the dynamic-address-translation
(DAT) facility. References to storage operands of
virtual-machine instructions are subject to the DAT
facility; translation is performed if the real CPU is
in the Be mode with a one in bit 5 of the real PSW. Such translations are performed under
control of the values in real control register 1 and
in bit positions 8-12 of real control register O. At the end of the detailed description of each
assist function is a table showing each field in
storage that is or may be referred to in performing
that assist function. For each field, the address
type is shown as real or logical. Only those fields
whose address type is logical are referred to by
addresses subject to the DAT facility. Low-A.ddress Protection
When any assist for VM/370 makes an operand
store access to virtual-machine storage during
execution of a virtual-machine instruction, low­
address protection is applied if the System/370 extended facility is installed and bit 3 of real
control register 0 is one. The contents of virtual
control register 0 have no effect on the application
of low-address protection. Low-address protection
is not applied to supervisor-call or program
interruptions in the virtual machine, to updates of
the virtual interval timer, or to references to VM/370 control blocks in the real machine when
virtual-machine instructions are being executed.
Low-address protection does apply to store accesses
in the normal manner for instructions in the
control-program assist. Processors No interlocking exists between the fetch and store
parts of an update to VM/370 control blocks or the
prefix-save areas (first 4K bytes of real storage) in
the virtual-machine assist or shadow-table-bypass
assist. The assist functions are not, in general,
designed for use with multiprocessing or an
attached processor. However, the purge-TLB
function of the shadow-table-bypass assist has
specific provision for operation under VM/370 running in attached-processor mode. DOS / OS Compatibility Facility
The virtual-machine-assist functions are not
invoked under control of the execute-local function
of the DOS/OS compatibility facility.
6 Virtual-\1achine Assist and Shadow-Table-Bypass Assist
General Conventions
The following control-program conventions are
observed.
Control-Block Alignment
The control blocks ECBLOK and VMBLOK, which
are referred to by functions in the virtual-machine
assist (VMA) and shadow-table-bypass assist (STBA), are assumed to be doubleword-aligned. If
the address MICCREG or MICVPSW, which is
used to access one of the control blocks, does not
specify the expected alignment, the result of an
attempt to access a field in ECBLOK or VMBLOK depends on several factors. For the supervisor-call
function of VMA, the supervisor-call interruption
may take place; for the shadow-table-validation
function of VMA or the page-fault-reflection
function of STBA, a program interruption for the
page-translation exception may take place; and for
any other VMA or STBA function, a program
interruption for a privileged-operation exception
may take place. Otherwise, the value of a fetched
field is unpredictable, and the storage locations
modified by a store access may be any locations in
the doublewords containing the misaligned field.
Also, an addressing exception that is recognized
may be for any part of the misaligned field.
Virtual PSW
Bits 0-15 of the virtual PSW are kept in the first
halfword of a doubleword. When the real PSW is
in the problem state, the PSW key, condition code,
program mask, and instruction-address parts of the
virtual PSW are kept in the corresponding parts of
the real PSW, and the problem-state bit of the
virtual PSW is kept in bit position 1 of control
register 6. When storing takes place in the virtual PSW field, only the first halfword is significant,
and the effect of the store operation on the
remaining six bytes is unpredictable.
Updating Swap-Table Entries
Bytes 0, 2, and 3 of a doubleword swap-table entry
may be updated by the reset-reference-bit fUnction and the set-storage-key function. The method of
updating may differ among models; individual
bytes, halfwords, a word, or the entire doubleword
of the entry may be fetched and subsequently
stored with the specified bytes changed.
Addressing Conditions
Fields in VM/370 control blocks are accessed in
assist functions with real addresses and with a key
of zero. If such an access is to a storage location
not available to the executing CPU, an addressing
condition occurs.
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