Alternate CS Field
14
IBM
Confidential
K 1010 PI-Sets the suppress-out latch on.
K - 0101 PI-Sets the operational-out control latch on.
K 0011 PI-The set or reset depends on the R register mask bits.
With the instruction K
=
0011 PI:
a.
If
the R register
0
bit is on
(1),
the MPX mask latch will be set
on.
b.
If
the R register 1 bit is on (1), the Selector Channel 1 mask will
be set on.
c.
If
the R register 2 bit is on (1), the Selector Channel 2 mask will
b@
set on.
d. If the R register 7 bit is on (1), external trap mask will be set on.
K - 1001 PI-The set or reset depends on the S register 0, 1 and 2 bits.
(See example 13B, page 29.)
a. With the above instruction, if the S register 0 bit is on (1), it sets
the XX high latch on.
b.
If
the S register 1 bit is on (1), it sets the X high latch on.
c. If the S register 2 bit is on (1), it sets the X low latch on. The XL,
XH, and XXH latches force the M register 1, 2, and 3 bits, which
in turn address a specific bump. The latches and M register bits
may appear in combinations.
CS - IIII
(K~FA)
This specifies the controls for MPX channel tag lines and conditions.
K - 0000 PI-Sets the command-start latch on.
K - 1000 PO-Sets the buss-out register from the R register.
K - 0100 PO-Sets the address-out-line on.
K 0010 PO-Sets the command-out-line on.
K - 0001 PO-Sets the service-out-line on.
NOTE
The FA register will frequently appear as a combination of
these.
Example: K
~
FA
K
=
1100 P1 which sets the buss-out CTRL,
address-out, and command-start latch on.
This field is activated by AS
= 1. It
controls the selector channel hardware.
CS
=
0110
(GUV~
GCD)
This specifies that the selector channel dak address register (GUV) is
gated to the selector channel count register (GCD).
CS
=
0111
(GR~GK)
This specifies that the GR register is gated to the selector channel protect
key register (GK).
CS
=
1000
(GR~GF)
This specifies that the GR register is gated to the selector channel flag reg-
ister (GF).

CS = 1001 (GR
~
GG)
This specifies that the GR register is gated to the selector channel command
register (GG).
CS
=
1010 (GR -. GU)
This specifies that the GR register is gated to the selector channel data ad-
dress register (GU).
CS
=
1011 (GR-'GV)
This specifies that the GR register is gated to the selector channel data ad-
dress register (GV).
CS = 1100 (K -. GH)
This specifies that the CK field values are decoded with gated K to GH to
determine specific selector channel functions.
*
K
*
K
O-Selector channel 1 and 2 machine reset.
I-Diagnostic and tag controls are set.
* K - 2-Tag control is reset.
K 7 -Chain detect is set.
*-Hardware is added for the Rand S diagnostic functions.
CS = 1101 (GI-'GR)
This specifies that the selector channel buss-in-line (GI) is gated tothe GR
register.
CS = 1110
(K~GB)
This specifies that the CK field values are decoded with gated K to GB to
determine specific selector channel functions.
K - O-Program Check
K - 1 and KP
=
O-Selector channel 1
and KP
=
I-Selector channel 2
K 2-0perational-out reset
K - 3-PCI flag is reset
K - 4-Selector channel interrupt is set
K
- 5-Channel control check
K
6-G R to zero is set
K - 7-CPU stored
K 8 and KP O-Count ready is reset
and KP I-Count ready is set
K 9 and KP O-Channel reset
and KP I-Poll control reset and channel reset
K 10 and KP O-Suppress-out is reset
and KP I-Suppress-out is set
K
-
11 and KP O-Poll control is reset
and KP I-Poll control is set
K
-
12-Select-out is reset
K - I3-Channel busy is set
K - 14-Halt 1-0 latch is set
K
-
15-Interface control check
NOTE
KP is K field parity bit.
IBM Confidential
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