CC
Field
C5
Field
12
IBM COllfidClltill/
CV
=
0001 (-)
This specifies a complement binary add. The B register data is comple-
mented at the ALD-B register entry.
CV
=
00 I 0 (+ 2)
This specifies a binary add under true-complement control. This is de-
pendent on the SO bit which is the true-complement latch.
SO
=
0-True add.
SO
=
I-Complement add.
CV
=
00 I I (± 3)
This specifies a decimal add under true-complement control. This is de-
pendent on the SO bit which is the true-complement latch.
SO 0-True add.
SO
=
I-Complement add.
This field controls the carry inputs and outputs of the ALD and the logic
functions (AND, OR, XOR).
CC = 0000 (0)
This decode specifies that the carry-input line is to be 0 and ignores the
carry out of the ALD.
CC
=
0001
(II
This decode specifies that the carry-input line is to be 1, and ignores the
carry out of the ALD. (See example I2A, page 27.)
CC
=;=
00 I 0 (.)
This decode specifies the AND function and ignores the carry out of the
ALD. The AND function requires a coincidence of bits to obtain an output.
(See example I2B, page 27.)
CC
=
0011 (0)
This decode specifies the OR function and ignores the carry out of the ALD.
The OR function requires a bit on either side to obtain an output. (See ex-
ample I2C, page 28.)
CC
=
0100 (0 C)
This decode specifies that the carry-input line is to be 0 and sets the S3 bit
to 1 if a carry results. The S3 bit is the carry latch. (See example I2D,
page 28.)
CC
=
0 I 0 I (I C)
This decode specifies that the carry-input line is to be 1 and sets the S3 bit
to 1 if a carry results. The S3 bit is the carry latch.
CC
=
0110 (C C)
This decode specifies the value of the carry latch onto the carry-input line
. and sets the S3 bit to 1 if a carry results. The S3 bit is the carry latch. (See
example I2E, page 28.)
CC = 0111 (V)
This decode specifies the XOR (Exclusive OR) function and ignores the
carry out of the ALD. The XOR function requires no coincidence of bits
to obtain an output. (See example I2F, page 28.)
This field controls the individual sets and resets of status in the S register.
It
also controls some I/O lines. CS has an alternate decoder activated by
the bit AS
=
1.
C5 = 0001
(LZ~
55)
This specifies that if the Low 4 bits of the Z buss are zeros, the S register

5 bit will be set on (1). If the Low 4 bits of the Z buss are not zeroes, the S
register 5 bit will be reset off (0). (See example 13A, page 29.)
C5
=
0010
(HZ~
54)
This specifies that if the High 4 bits of the Z buss are zeros, the S register
4 bit will be set on (1). If the High 4 bits of the Z buss are not zeros, the S
register 4 bit will be reset off (0). (See example 13A, page 29.)
CS
=
0011
(LZ~
55,
HZ~
54)
This specifies that if the High-Low 4 bits of the Z buss are zeros or any
combination thereof, the corresponding S register 4 and 5 bits will be set
on (1). If the High-Low 4 bits of the Z buss are not zeroes or any combina-
tion thereof, the corresponding S register 4 and 5 bits will be reset off (0).
(See example 13A, page 29.)
C5
=
0100 (0
~
54, 55)
This specifies that the S register 4 and 5 bits will be reset off (0).
CS
=
0101 (Treq
~
51)
This specifies that if a 1050 request occurs, the S register 1 bit will be set
on
(1).
C5
=
0110
(O~
50)
This specifies that the S register
0
bit (true-complement latch) will be re-
set off (0).
C5
=
0111
(I
~
50)
This specifies that the S register 0 bit (true-complement latch) will be set
on (1).
C5 = 1000
(O~
52)
This specifies that the S register 2 bit will be reset off (0).
C5
=
1001
(ANSNZ~52)
This specifies that if the Z buss (results of an arithmetic statement) is non-
zero, the S register 2 bit will be set on (1). If the Z buss is zero, the S reg-
ister 2 bit would not be reset. (See example 13A, page 29.)
NOTE
A special function of the above decode takes place if the
suppress-machine trap latch is on (1), the CPU check
switch is in diagnostic mode, and the Z buss is not zero (0);
the machine is forced to a hard stop.
C5 = 1010 (0
~
56)
This specifies that the S register 6 bit will be reset off (0).
CS
=
1011 (I
~
56)
This specifies that the S register 6 bit will be set on (1).
C5
=
1100 (0
~
57)
This specifies that the S register 7 bit will be reset off (0).
C5
=
1101
(I~57)
This specifies that the S register 7 bit will be set on (1).
C5
=
1110 (K
~
FB)
This specifies the controls for numerous MPX channel conditions.
K - 1100 PI-Sets the MPX channel interrupt latch on.
K = 0110 PI-Sets the MPX operation latch on.
IBM
ConfiJ~ntitll
13