CU Field
Alternate CU Field
CA Field
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IBM Confidential
CM
=
0111
(GUV~
MN)
This decode sends a read call to memory and specifies an address for the
MN register. This decode turns on the allow write latch and gates the GUY
(selector channel) register address to the MN register.
It
also addresses that
location of either the main storage or the local storage. The data from the
addressed location is read out and into the R register.
If
one read follows
another read, the second read is ignored (no read call), but the GUY ad-
dress is gated to the MN register. (See example 2C, page 19.)
This field specifies the area of memory to be addressed (MS, LS and MPX),
depending on the value of the CM field.
CU ..:.- 0000 (MS)
If
the CM decode is any combination of conditions 3 through 7, it specifies
that the machine is addressing the main storage. The R register is assumed
to be the destination for the data from memory. (See example 3A, page 21.)
CU
=
0001
(LS)
If
the CM decode is any combination of conditions 3 through 7, it specifies
that the machine is addressing local storage (CPU Bump). The R register
is assumed to be the destination for the data from memory. (See example
3B, page 21.)
CU
=
0010
(MPX)
If
the CM decode is any combination of conditions 3 through 7, it specifies
that the machine is addressing MPX (UCW Bump). The R register is as-
sumed to be the destination for the data from memory. (See example 3C,
page 22.)
CU
=
0011
(MILS)
This decode is a function of the macroinstruction format and specifies the
LS (CPU Bump) if the G register 0 and 1 bits are off (0).
If
either the G
register 0 and/or 1 bits are on (1), main storage is selected. The R register
is assumed to be the destination for data from memory. (See example 3D,
page 22.)
Activated by CM
=
0000,0001 or 0010.
CU = 0001 (Use GR)
This decode specifies that the selector channel data register (GR) will be
the destination for data from memory. (See example
4A,
page 22.)
CU
=
0010
(K~W)
This decode is used for changing modules.
It
uses the CK field to specify the
value.
It
does not change the W3 bit. (See example 4B, page 23.)
CU
=
0011
(FWX~WX)
This decode gates the FWX register (backup ROSAR) into the WX regis-
ter (ROSAR).
It
restores the link address of a microprogram routine dis-
rupted by an I/O trap. (ROSAR-Read Only Storage Address Register.)
(See example 4C, page 23.)
This field names the desired input to the A register.
CA
=
0000
(FT)
This decode specifies the MPX tags-in-buss (FT) as the input to the A reg-
ister. The A register parity check is blocked. (See example 5, page 24.)
CA
=
000 I (TT)
This decode specifies the 1050 tags-in-buss (TT) as the input to the A reg-
ister. The A register parity check is blocked. (See example 5, page 24.)

Alternate CA Field
CA
=cc
0 I 00 (S)
This decode specifies the S register as the input to the A register. The A
register parity check is blocked. (See example 5, page 24.)
CA =
0101 (H)
This decode specifies the H register as the input to the A register. The A
register parity check is blocked. (See example 5, page 24.)
CA
=
0110 (FI)
This decode specifies the MPX buss-in-line (FI) as the input to the A reg-
ister. (See example 5, page 24.)
CA =
0111 (R)
This decode specifies the R register as the input to the A register. (See ex-
ample 5, page 24.)
CA
=
1000 (D)
This decode specifies the D register as the input to the A register. (See ex-
ample 5, page 24.)
CA =
1001 (L)
This decode specifies the L register as the input to the A register. (See ex-
ample 5, page 24.)
CA =
1010
(G)
This decode specifies the G register as the input to the A register. (See ex-
ample 5, page 24.)
CA =
1011 (T)
Thil decode specifies the T register as the input to the A register. (See ex-
ample 5, page 24.)
CA =
1100 (V)
This decode specifies the V register as the input to the A register. (See ex-
ample 5, page 24.)
CA =
1101 (U)
This decode specifies the U register as the input to the A register. (See ex-
ample 5, page 24.)
CA
=
1110
(J)
This decode specifies the
J
register as the input to the A register. (See ex-
ample 5, page 24.)
CA
=
1111
(I)
This decode specifies the I register as the input to the A register. (See ex-
ample 5, page 24.)
Activated by AA
=
1
CA =
0000
(F)
This decode specifies the external interrupt register (F), in the complement
form, as the input to the A register. (See example 5, page 24.)
CA
=
0001 (SFG)
This decode specifies the console switches F and G as the input to the A reg-
ister. (See example 5, page 24.)
CA
=
0010 (MC)
This decode specifies the machine check register (MC) as the input to the
A register. The A register parity check is blocked. (See example 5, page
24.)
CA
=
0100 (C)
This decode specifies the interval timer register (C) as the input to the A
register. The A register parity check is blocked. (See example 5, page 24.)
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