I I TYPE MODULE I SiC I External Aachine Check I/O Prograll Check DMKSVCIN DMKPSAEI DMKMCHIN DMKIOSIN DMKPRGIN Interrupt Handler Modules , I Interrupt Froll Action/Module Unknown channel Unsolicited device end
and for:
Console 3270s on bisync lines
Local 3270, 3158, and 3066 consoles Unit record, real spooling
Solicited device end
Channel error
Monitor tape I/O operation
Dedicated device error - DASD Dedicated device error -Tape 3270 bisync line and channel errors
R
ecoverab Ie Unrecoverable /0 Interrupt Handler (DMKIOS) Actions
Reason for Prograll Check
Bor.al paging Paging - virtual machine in EC lIode
Supervisor State Privileged instruction DIAGNOSE Tillers Virtual Machine I/O console
unit record, virtual spooling
Ignored - DMKDSPCH Build rOBLOR DMKCBSIB DMKRGA or DMKRGB DMKGRF DMKRSPEI DMKSTKIO D!KCCHBT DMK!OBIO DMKDASER D!KTAPER DMKBSG D!KSTKIC DMKIOERR Module DMKPTRAN DMKVAT D!KDMP DMKPRVLG DMKHVC DMKTMR DMKVSIEX DMKVCBEI D!!KVSPEI Prograll Check Interrupt Handler (D!!KPRG) Actions
Figure 14. Overview of Interruption Handling NOB-I/O PRIVILEGED INSTRUCTIONS I I I D!!KPRVLG siaulates valid non-I/O privileged instructions and returns
control to DMKDSPCH. For invalid non-I/O privileged instructions, the
routine sets an invalid interruption code and reflects the interruption
to the virtual aachine. For the privileged instructions (SCK, SCKC, STCKC, SPT, and STPT) that affect the TOD clock, CPU tiller, and TOD clock coaparator, control is transferred to D!!KT!!R by D!!KPRVLG. Other instructions that are sillulated are LPSW, SS!!, SSK, ISK, IPTE, and DIAGNOSE. CP Introduction 1-47

Although the CS and CDS instructions are nonprivileged, they are not
part of the standard instruction set on IBft system/370 ftodels 135,
135-3, 138, 145, 145-3, and 148; Vft/370 simulates these instructions on
these models that do not have the optional hardware feature installed. System/370 BC .ode non-I/O privileged instruction simulation includes
the following:
Code SCK SCICC STCKC SPT STPT STRSft STOSft STIDP STIDC LCTL STCTL LRA
RRB
PTLB IPIC SPICA 1-48
Definition Set-Clock Set Clock Comparator Store Clock Comparator Set CPU Tiaer Store CPU "Timer Store and AND System ftask Store and OR Systea ftask Store CPU Identification Store Channel Identification
Load Control Store Control
Load Real Address
Reset Reference Bit
Purge Table Look-aside Buffer
Insert PSi Key Set PSi Key Prom Address IBft Vft/310 System Logic and Problem Determination--Voluae 1