last CCW used and provides its residual by'te count,
thus indicating the extent of main storage used.
Both the channel and the device can provide indica­
tions of unusual conditions with Channel End. The Channel End/Device End condition can be accompanied b,,' ('rror indications from the device.
Facilities are provided for the program to initi­ 'ite execution of a chain of operations with a single Start L o. When the chaining flags in the current ccw specify command chaining and no unusual con­
ditions have been detected in the operation, the
receipt of the Channel End/Device End signal causes
the channel to fetch a new CCW and to initiate a new
command at the devicc. A chained command is ini- Liated by iHeans of the same sequenCe of signals .j. 1 T / f \ !. -- 4- r - ('., r>. ,.." ,-, • 1.-. n .f ""\< ... ,.. ... f rt ro, Y'V"I " "" r1 ,....., ... n ,... ; fi n rl ....1. ,. 1 " J .J. -" ,_-+ ". -_" ,.. £ "--- ..L -"-.. '-- _ • _ --"" ...... ...... 1:_ -_ "-"" -=- -"- ........... by Start 1/ O. The ending signals that occur at the
termination of an operation initiated by a CCW specifying command chaining are not made available
to the program when another operation is initiated
by the command chaining; the channel continues
execution of the channel program. If, however, an
unusual condition has been detected, the ending
signals cause suppression of command chaining
and termination of the channel program.
Conditions that initiate I/O interruptions are
asynchronous to activity in the CPU, and more than
one condition can occur at the same time. The
channel and the CPU establish priority among the
conditions so that only one interruption request is
processed at a time. The conditions are preserved
in the I/O devices and subchannels until accepted by
the CPU. Execution of a 2703 operation, or chain of
operations, thus involves up to three levels of parti­
cipation:
1. Except for the effects caused by the integration
of CPU and channel equipment, the CPU is busy
for the duration of execution of Start I/O, which lasts at most until the addressed I/O device responds to the first command.
2. The subchannel is busy with the execution from
the initiation of the operation at the I/O device
until the Channel End condition for the last
operation of the command chain is accepted by
the CPU. 3. The 2703 is busy from the initiation of the first
command until the Channel End/Device End condition associated ''lith the last oppration is
accepted or cleared by the CPU. A pendlllg Channel End/Device Enu vunuition eauses the associated device to appear busy and normaE,; blocks all communications through the sub- l" ("<ich ,;!_;1)channel i"O to thE' ; ()ncC' 1 (' the sub- channel, no additional assignment can be made to
this subchannel. COMMUNICA TIONS- LINE ADDRESSING
The 2703 appears as a control unit to the IBM System/360. Two individual 2703's can be attached
to the multiplexer channel with each 2703 occupying
the place of one control unit. Actuallv, eight 2703' s
can be attached to the same multiplexer channel;
however, channel-addressing restrictions normally
make this impractical.
Each communications line attached to the 2703 is identified by a unique I/O address. This address
is specified by a H>-bit binary number that appears
. " , " r· ", r 11 T Jr-,. i ," I· 111 aUuJ"e>::>::, 11l:1U U1 Llle v 11l>::>Ll UCLHJi1. Vi 2703 operation, this I/O address consists of two
parts: a channel address, and a communications­
line address. The eight high-order bit positions of
this field specify the channel address. However,
since only channels 0-6 are available to the 2703, the five high-order positions of this byte are unused
for channel addressing for all 2703 operations. The
low-order eight bits specify the communications line
attached to the 270-3. The basic I/O-address format
for the System/360 is as follows: 0000 Oxxx xxxx xxxx Byte 1 Byte 2
1. Channel Address
(restricted to 0-6 range)
2. 2703 Line Address
The complete addresses needed by the System/360
to address each of ten half-duplex communications
lines connected to a 2703 (which, in turn, is
connected to a specific multiplexer channel) are: 0000 Oxxx 0000 0000 0000 Oxxx 0000 0101 0000 Oxxx 0000 0001 0000 Oxxx 0000 0110 0000 Oxxx 0000 0010 0000 Oxxx 0000 0111 0000 Oxxx 0000 0011 0000 Oxxx 0000 1000 0000 Oxxx 0000 0100 0000 Oxxx 0000 1001 The assignment of addresses to particular start/
stop lines is done in groups of eight and must be
done in a particular manner when configurating a
system. For synchronous type lines, address are done in groups of four lines.
The 2703 requires that the lowest address within thp hpP'in at a sDecific address boundary. The -:re then by group, as previously
indicated, consecuti"vely from the low-address
boundary to the highest valid address (or some group
increment below this address). The specific cons i­ ckrations necessary \yhen assigning 270:3 addresses arc coycrcd in detail under "Addrpss-Assignment Considerations. " I

A specific line base is assigned as the first line
base within the continuous span of addresses. Then
a line set of eight line adapters is added for this line
base. As many lines as desired (up to eight lineE for start/ stop, or four lines for synchronous opera­
tion) are attached to this line set. Addresses are
assigned to all eight lines even if lines are not attached. ¥lhen the first line base is filled--or has as many lines
attached as desired--the addresses are assigned to the
second line base in the same manner. Similarly, ad­
dresses are assigned to the third line base if it is
attached to the 2703.
If two 2703's are placed on the channel, the
second 2703 may be placed with its lowest address
in the next increment of 16 not assigned to the first
2703. Address assignment has no bearing on the
priority of any particular line. This is a function of
the type of line base only.
Address-Assignment Considerations
Numerous things should be considered when deter­
mining the 2703 address assignments. However,
all these various items can be associated with the
following list of major considerations involving
address assignment:
1. A multiplexer channel can accommodate a
maximum of 256 individual addresses. NOTE: Each address is associated with an individual sub channel
within the multiplexer channel. ThE: c:apabilitics of a specific channel are
dictated by the IBM System/360 processor
model employed and the available core storage.
Refer to "Maximum Lines Available by
Processor Model. " 2. The specific address range available for
assignment is 0 to 255.
3. Any one 2703 is limited to a maximum of 176
individual addresses (or lines).
4. The low-address boundary for address assign­
ment should be either 0 or a 16-unit increment
thereof (for examp!e--1&, 32, or 48). NOTE: A boundary of 48 should be used if convenient. This start­ ing number reserves sufficient positions to allow the channel ;,tt:ichmcnt of other devices with standard assigned addresses (for example, the standard assigned address for the 1050 Docu­
mentary Console is 31 or'1F'*). This also simplifies installa­
tion, since the low-boundary address of 48 is prewired before
shipping.
5. The high-address boundary must be an even
increment of either 8 (for startl stop) or 4
(for synchronous) from the low-address
boundary within the 2703.
6. The 10\\lest address within the 2703 is always
assigned as the wrap address. The wrap i< , , is Hexadecimal representation.
address is the address of the line used to read
data back to the channel from any line issued
the Wrap command. The wrap address and its
associated line can be used for normal trans­
mission at all times, except when the 2703
is being checked with a Wrap command. Refer
to "Automatic Wrap-around" under "Program­ ming Considerations. " Maximum Lines Available by Processor Model
Each half-duplex communications line requires a
separate subchannel within the multiplexer channel.
The addresses for these lines are assigned sequen­
tially on the 2703, normally starting at address 16.
(See item 4 under "Address-Assignment Considera­
tions. ") A second 2703 can be attached to the
same channel. The low -address bounda.ry of the
second 2703 is the first available address in the next
increment of 16 above the first 2703. Different
numbers of subchannels are available on the IBM
System/360 Models 30, 40, 50, 65, and 75. The
maximums are given in the following as a function
of the processor and the minimum core-storage
size. In the case of the mM 2780 Multiplexer
Channel, the number of subchannels is not dependent
on the core storage available.
Processor Number of Minimum Core-StoragE
Model Sub channels
Model C 30 Model D 30 Model ElF 30 Model D 40 Model E 40 Model F 40 Model G/H 40 Model F 50 Model G 50 Model HII 50 Processor Model
with 2870
Model 65
Model 75
32
96
224
16
32
64
128
64
128
256
Number of
Subchannels
192
192
Size (Bytes)
8K
16K
32K-64K and
Feature #5250* 16K
32K
64K
128K
64K
128K
256K-512K and
Feature #5250* *Additional Multiplexer SubchalUlels special feature
13