By TNL:
but a right-shift of one digit position may be called
for. The intennediate-quotient characteristic is ad
justed for the shift. The intennediate-quotient frac
tion is subsequently truncated to the proper result
fraction length.
The sign of the quotient is determined by the
rules of algebra, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-overflow exception is recognized
when the final-quotient characteristic exceeds 127
and the fraction is not zero. The operation is com
pleted, and a program interruption occurs. The result
is normalized, the sign and fraction remain correct,
and the characteristic is 128 less than the correct
value.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under
flow mask bit is zero, a program interruption does
not
by making the quotient a true zero.
Exponent underflow is not signaled when an op
erand characteristic becomes less than zero during
prenonnalization or the intennediate-quotient char
acteristic is less than zero, but the final quotient can
be
flow.
A floating-point divide exception is recognized
when the divisor fraction is zero. The operation is
suppressed, and a program interruption for floating
point divide occurs.
When the dividend fraction is zero, the quotient is
made a true zero, and a possible exponent overflow
or exponent underflow is not recognized. A division
of zero by zero, however, causes the operation to be
divide to occur.
4, or 6; otherwise, a specification exception is recog
nized.
The code remains unchanged.
installed)
164
Floating-Point Divide
Halve
HER Rl,R2
[RR,
34
o 8 12 15
HDR Rl,R2
[RR, Long Operands]
24
o 8 12 15
The second operand is divided by 2, and the normal
ized quotient is placed in the first-operand location.
The fraction of the second operand is shifted right
one bit position, placing the contents of the low
order bit position· into the high-order bit position of
the guard digit and introducing a zero into the high
order bit position of the fraction. The intennediate
result is subsequently normalized, and the normal
ized quotient is placed in the first-operand location.
The guard digit participates in the normalization.
The sign of the quotient is the same as that of the
second operand, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under
flow mask bit is zero, program interruption does not
take place; instead, the operation is completed by
making the quotient a true zero.
When the fraction of the second operand is zero,
the result is made a true zero, and no exceptions are
recognized.
The Rl and R2 fields must designate register
4, or 6; otherwise, a specification exception is recog
nized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Specification
Exponent Underflow