1. An immediate command specifying no chaining
may result in setting condition code ° rather
than c:ondition code 1.
2. Multiple PCI interruptions may be generated
for a single CCW with the PCI flag.
3. Since CCWs may be refetched, programs
which dynamically modify CCWs may be af­
fected.
4. The residual count in the CSW reflects only the
last execution of the command and does not
necessarily reflect the maximum storage used
in previous executions.
252 System/370 Principles of Operation
Logout on Channel Data Check
In System/360, logout is not permitted on channel
data check. System/370 permits logout to occur
when the channel causes an I/O interruption with
the channel-data-check indication.
Channel Pref etching
In System/360, on an output operation as many as
16 bytes may be prefetched and buffered; similarly,
with data chaining specified, the channel may pre­
fetch the new CCW when up to 16 bytes remain to
be transferred under control of the current CCW. In System/370, the restriction of 16 bytes is removed.

The following four lists are of instructions arranged
by name, mnemonic, operation code, and feature.
Some models may offer instructions not appearing in
the lists, such as those provided for emulation or as
part of special or custom features ..
The operation code 00, with a two-byte instruc­
tion format, and the set of sixteen 16-bit operation
The listings in the Characteristics and Code columns mean:
A Access exceptions
A1 Addressing exception only A2 Addressing and translation-specification exceptions only B PER branch event C Condition code is set CK CPU-timer and clock-comparator feature
D
Data exception DC Direct-control feature
DF Decimal-overflow exception
DK Decimal-divide exception
Appendix C. Lists of Instructions
codes B2EO to B2EF, with a four-byte instruction
format, are allocated for software uses where indica­
tion of invalid operation is required. It is improbable
that these operation codes will ever be assigned to
an instruction implemented in the CPU. DM Depending on the model, DIAGNOSE may generate various program exceptions
and may change the condition code
E Exponent-overflow exception
EX Execute exception
FK Floating-point-divide exception FP Floating-point feature IF Fixed-point-overflowexception II Interruptible instruction I K Fixed-point-divide exception
L New condition code loaded LS Significance exception
M Privileged-operation exception MO Monitor event MP Multiprocessing feature PD Decimal feature PK PSW-key-handling feature
R PER general-register-alteration event
RR RR instruction format RS RS instruction format
RX RX instruction format S S instruction format SI SI in.struction format SO Special-operation exception SP Specification exception SS SS instruction format ST PER storage-alteration event SW Conditional-swapping feature
TR Translation feature
U
Exponent-underflow exception XP Extended-precision floating-point feature
Bits 8-14 of the operation code are ignored +- Bits 8-15 of the operation code are ignored
$ Causes serialization $1 Causes serialization when the R
1 and R
2 fields contain all ones and all zeros, respectively. Appendix C. Lists of Instructions 253